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Part: 7C33128PFS36A
Category:
Description:
Company: Alliance Semiconductor
Datasheet: Download 7C33128PFS36A datasheet File size : 137 kB
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January 2001 Preliminary Information
®
7C33128PFS32A 7C33128PFS36A
3.3V 128K X 32/36 pipeline burst synchronous SRAM Features
· Organization: 131,072 words × 32 or 36 bits · Fast clock speeds to 166 MHz in LVTTL/LVCMOS · Fast clock to data access: 3.5/3.8/4.0/5.0 ns · Fast OE access time: 3.5/3.8/4.0/5.0 ns · Fully synchronous register-to-register operation · Single register "Flow-through" mode · Single-cycle deselect - Dual-cycle deselect also available (AS7C33128PFD32A/ AS7C33128PFD36A) · Pentium®* compatible architecture and timing · Asynchronous output enable control · Economical 100-pin TQFP package · Byte write enables · Multiple chip enables for easy expansion · 3.3 core power supply · 2.5V or 3.3V I/O operation with separate VDDQ · 30 mW typical standby power in power down mode · NTDTM* pipeline architecture available (AS7C33128NTD32A/ AS7C33128NTD36A)
Logic block diagram
LBO CLK ADV ADSC ADSP A[16:0] 17 CLK CE CLR D CE Address register CLK D Q0 Burst logic Q1 17 Q
Pin arrangement
A6 A7 CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A8 A9 128K × 32/36 Memory array 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
15
17
GWE BWE BWd
DQd Q Byte write registers CLK D DQc Q Byte write registers CLK D DQb Q Byte write registers CLK D D Qa Q Byte write registers CLK D Enable CE register CLK Power down D Enable Q delay register CLK Q
36/32
36/32
BWc
BWb
BWa CE0 CE1 CE2
4
ZZ
OE FT DATA [35:0] DATA [31:0]
Note: Pins 1,30,51,80 are NC for ×32
Selection guide
AS7C33128PFS32A AS7C33128PFS32A AS7C33128PFS32A AS7C33128PFS32A 166 150 133 100 Units Minimum cycle time Maximum clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)
* ®
6 166 3 .5 475 130 30
6.7 150 3.8 450 110 30
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
OE Output registers CLK
Input registers CLK
DQPc/NC DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc FT VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd/NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
TQFP 14 × 20 mm
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb/NC D Qb D Qb VDDQ VSSQ D Qb D Qb D Qb D Qb VSSQ VDDQ D Qb D Qb VSS NC VDD ZZ D Qa D Qa VDDQ VSSQ D Qa D Qa D Qa D Qa VSSQ VDDQ D Qa D Qa DQPa/NC
7.5 133 4 425 100 30
10 100 5 325 90 30
ns MHz ns mA mA mA
Pentium is a registered trademark of Intel Corporation. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners.
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Copyright © Alliance Semiconductor. All rights reserved.
7C33128PFS32A 7C33128PFS36A
®
Functional description
The AS7C33128PFS32A and AS7C33128PFS36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology. Timing for these devices is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP (TMS320C6X), and PowerPCTM*-based systems in computing, datacomm, instrumentation, and telecommunications systems. Fast cycle times of 6/6.7/7.5/10 ns with clock access times (tCD) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High. Burst operation is selectable with the LBO input. With LBO unconnected or driven High, burst operations use a Pentium® count sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPCTM and many other applications. , Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/ 36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s). BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to the next burst address if BWn and ADV are sampled Low. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow. · ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC. · WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High). · Master chip enable CE0 blocks ADSP, but not ADSC. AS7C33128PFS32A and AS7C33128PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.
*PowerPCTM is a tradenark International Business Machines Corporation.
Capacitance
Parameter Input capacitance I/O capacitance S ymbol CI N CI / O Signals Address and control pins I/O pins Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 U nit pF pF
Write enable truth table (per byte)
GWE L H H H
Key:
BWE X L H L
BWn X L X H
WEn T T F* F*
X = Don't Care, L = Low, H = High, T = True, F = False; *= Valid read; n = a, b, c, d; WE, WEn = internal write signal.
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7C33128PFS32A 7C33128PFS36A
®
Signal descriptions
I/ Signa l O CLK I A0A16 I DQ[a,b,c,d] I/O CE0 CE1, CE2 ADSP ADSC ADV GW E B WE I I I I I I I Properties CLOCK SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC ASYNC STATIC default = HIGH STATIC ASYNC Description Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock. Address. Sampled when all chip enables are active and ADSC or ADSP are asserted. Data. Driven as output when the chip is enabled and OE is active. Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information. Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe processor. Asserted LOW to load a new bus address or to enter standby mode. Address strobe controller. Asserted LOW to load a new address or to enter standby mode. Advance. Asserted LOW to continue burst read/write. Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d] control write enable. Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs. Write enables. Used to control write of individual bytes when GWE = HIGH and BWE = Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write cycle. If all BW[a:d] are inactive the cycle is a read cycle. Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read mode. Count mode. When driven High, count sequence follows Intel XOR convention. When driven Low, count sequence follows linear convention. This signal is internally pulled High.18 Flow-through mode.When low, enables single register flow-through mode. Connect to VDD if unused or for pipelined operation. Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
BW[a,b,c,d] I OE LBO FT ZZ I I I I
Absolute maximum ratings
Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation DC output current Storage temperature (plastic) Temperature under bias Symbol VDD, VDDQ VIN VIN PD IOUT Tstg Tbias Min 0.5 0.5 0.5 65 65 Ma x +4.6 VDD + 0.5 VDDQ + 0.5 1.8 50 +150 +135 U nit V V V W mA o C o C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
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7C33128PFS32A 7C33128PFS36A
®
Synchronous truth table
CE0 H L L L L L L L L X X X X H H H H L X H X H CE1 X L L X X H H H H X X X X X X X X H X X X X C E2 X X X H H L L L L X X X X X X X X L X X X X ADSP X L H L H L L H H H H H H X X X X H H X H X ADSC L X L X L X X L L H H H H H H H H L H H H H ADV X X X X X X X X X L L H H L L H H X L L H H
WEn1
OE X X X X X L H L H L H L H L H L H X X X X X
Address accessed NA NA NA NA NA External External External External Next Next Current Current Next Next Current Current External Next Next Current Current
CLK L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H
Operation Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Cont. read Cont. read Suspend read Suspend read Cont. read Cont. read Suspend read Suspend read Begin write Cont. write Cont. write Suspend write Suspend write
DQ Hi - Z Hi - Z Hi - Z Hi - Z Hi - Z Hi-Z2 Hi-Z Hi-Z2 Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z D3 D D D D
X X X X X X X F F F F F F F F F F T T T T T
Key: X = Don't Care, L = Low, H = High. 1 See "Write enable truth table"on page 2 for more information. 2 Q in flow through mode. 3 For write operation following a READ, OE must be HIGH before the input data set up time and held HIGH throughout the input hold time.
Recommended operating conditions
Parameter Supply voltage 3.3V I/O supply voltage 2.5V I/O supply voltage Address and control pins I/O pins Ambient operating temperature Symbol V DD V SS VDDQ V SSQ VDDQ V SSQ VIH VIL VIH VIL TA Min 3.135 0.0 3.135 0.0 2.35 0.0 2.0 0.5* 2.0 0.5 0
*
Nominal 3.3 0.0 3.3 0.0 2.5 0.0
Max 3 .6 0 .0 3 .6 0 .0 2 .9 0 .0 VDD + 0.3 0 .8 VDDQ + 0.3 0 .8 70
Unit V V V V V °C
Input
voltages
* VIL min = 2.0V for pulse width less than 0.2 × tRC. Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
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7C33128PFS32A 7C33128PFS36A
®
TQFP thermal resistance
Description Thermal resistance (junction to ambient)* Thermal resistance (junction to top of case)*
* This parameter is sampled.
C onditi ons Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/ JESD51
S ym bol JA JC
Typical 46 2.8
U nits °C/W °C/W
DC electrical characteristics
166 Parameter Input leakage current* Output leakage current Operating power supply current Symbol |ILI| |ILO| ICC I SB Standby power supply current ISB1 ISB2 Output voltage VOL VOH Test conditions VDD = Max, VIN = GND to VDD OE VIH, VDD = Max, VOUT = GND to VDD CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax, IOUT = 0 mA Deselected, f = fMax, ZZ VIL Deselected, f = 0, ZZ 0.2V all VIN 0.2V or VDD 0.2V Deselected, f = fMax, ZZ VDD 0.2V All VIN VIL or VIH IOL = 8 mA, VDDQ = 3.465V IOH = 4 mA, VDDQ = 3.135V 150 133 100 Min Max Min Max Min Max Min Max Unit 2.4 2 2 475 130 30 30 0.4 2.4 2 2 450 110 30 30 0 .4 2.4 2 2 425 100 30 30 0.4 2.4 2 2 325 90 30 30 0.4 V mA µA µA mA
* LBO pin has an internal pull-up and input leakage = ±10 µa. Note: ICC given with no output loading. ICC increases with faster cycles times and greater output loading.
DC electrical characteristics for 2.5V I/O operation
166 Parameter Output leakage current Output voltage Symbo l |ILO| VOL VOH Test conditions OE VIH, VDD = Max, VOUT = GND to VDD IOL = 2 mA, VDDQ = 2.65V IOH = 2 mA, VDDQ = 2.35V 150 133 100 Min Max Min Max Min Max Min Max Unit 1 1 .7 1 0.7 1 1.7 1 0.7 1 1.7 1 0 .7 1 1.7 1 0.7 µA V
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