Details, datasheet, quote on part number: AS5LC2M16
DescriptionLow Power Asynchronous Pseudo SRAM For Mobil Specific Applications, 32M, 2Mx16
CompanyAlliance Semiconductor
DatasheetDownload AS5LC2M16 datasheet


Features, Applications

X 16 IntelliwattTM Super Low-Power CMOS Pseudo Static SRAM Features

AS5LC2M16 IntelliwattTM active power circuitry Industrial, commercial and extended temperature ranges Organization: × 16 bits to 3.3V power supply range Fast access times 55/70/85 ns Low power consumption: ACTIVE 150 mW max at 3.3V and 55 ns Low power consumption: STANDBY 330 µW max at 3.3V SRAM compatible pinout and functionality Equal access and cycle times 4 word Page Read Operation Easy memory expansion with CS2, OE inputs Known good die availability Smallest footprint package - 48-ball FBGA; x 8.0 mm ESD protection 2000 volts Latch-up current 200 mA

VCC Range Min (V) 2.7 Typ (V) 3.0 Max (V) 3.3 Speed (ns) 70 85 Power Dissipation Operating (ICC1) Max (mA) 5 Standby (ISB1) Max (µA) 100

The is a low-power single transistor (1T) CMOS 33,554,432-bit Pseudo Static Random Access Memory (PSRAM) device organized × 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) 55/70/85 ns are ideal for low-power applications. Active high and low chip selects (CS1 and CS2) permit easy memory expansion with multiple-bank memory systems. The device can also be put into standby mode when deselected (CS1 is high CS2 is low, or UB and LB are high). The input/ output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected CS1 is high CS2 is low, or UB and LB are high), outputs are disabled (OE High), UB and LB are disabled (UB, LB High), or during a write operation CS1 is low CS2 is high and WE Low). Writing to the device is accomplished by taking Chip Selects CS1 Low, CS2 High and Write Select (WE) input Low. If Byte Low Select (LB) is Low, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A20). If Byte High Select (UB) is Low, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A20). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). Reading from the device is accomplished by taking Chip Select CS1 Low, CS2 High and Output Enable (OE) Low while forcing the Write Enable (WE) High. If Byte Low Enable (LB) is Low, then data from the memory location specified by the address pins will appear I/O7. If Byte High Enable (UB) is Low, then data from memory will appear to I/O15. These devices provide multiple power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0­I/O7, and UB controls the higher bits, I/O8­I/O15. All chip inputs and outputs are CMOS-compatible, and operation is from a single to 3.3V supply. Device is available in the JEDEC 48-ball FBGA package.

Parameter Voltage on VCC relative to VSS Voltage on any I/O pin relative to GND Power dissipation Storage temperature (plastic) Temperature with VCC applied DC output current (low) Symbol VtIN VtI/O PD Tstg Tbias IOUT Min Max VCC + 0.5 VCC Unit V W

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC Recommended operating condition (over the operating range)

Parameter Vcc VOH VOL VIH VIL ILI ILO ICC1 Description Supply voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Average VCC Operating Supply Current at 1 MHz Test Conditions IOH = ­1.0mA IOL = 2.1mA GND < VIN < VCC GND VO < VCC; Outputs High Z IOUT CS2> VCC-0.2V, VIN 0.2V or VIN > VCC-0.2V IOUT f = fMax, CS1 = VIL, CS2 = VIH, VIN = VIL or VIH Iout = 0mA, tPC = min, CS1 = VIL, CS2 = VIH, VIN = VIH or VIL, page address cycling CS1 > VCC UB = LB. > Vcc -0.2V. [Other inputs = VCC or VSS] 55ns ICC2 Average VCC Operating Supply Current 85ns 100


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