Details, datasheet, quote on part number: AS6UA51216
CompanyAlliance Semiconductor
DatasheetDownload AS6UA51216 datasheet


Features, Applications

3.6V 512K16 IntelliwattTM low power CMOS SRAM with one chip enable Features

AS6UA51216 IntelliwattTM active power circuitry Industrial and commercial temperature ranges available Organization: 524,288 words 16 bits 100 ns Low power consumption: ACTIVE at 3.6V and at 2.7V and 2.3 V and 100 ns Low power consumption: STANDBY 72 W max 41 W max 28 W max 2.3V 1.2V data retention Equal access and cycle times Easy memory expansion with CS, OE inputs Smallest footprint packages - 48-ball FBGA 400-mil 44-pin TSOP II ESD protection 2000 volts Latch-up current 200 mA

Note: A "MODE" pad to be placed between pins 33 and 34 and 11 and 12, shorted. The bonding of this pad to VCC or VSS configures the device. There should only be 44+2+2 pads on the chip. Two extra VCC to separate out Array from Peripheral and Two-Mode Pads.

VCC Range Product AS6UA51216 Min (V) 1.65 Typ2 (V) 2.5 2.0 Max (V) 2.7 2.3 Speed (ns) 70 100 Power Dissipation Operating (ICC1) Max (mA) 2 1 Standby (ISB2) Max (A) 15 12

The is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288 words 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) 55/70/100 ns are ideal for low-power applications. Active high and low chip enables (CS) permit easy memory expansion with multiple-bank memory systems. When CS is high, or UB and LB are high, the device enters standby mode: the AS6UA51216 is guaranteed not to exceed 72 W power consumption at 3.6V and at 2.7V and 70 ns; at 2.3V and 100 ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption. A write cycle is accomplished by asserting write enable (WE) and chip enable (CS) low, and UB and/or LB low. Data on the input pins O16 is written on the rising edge of WE (write cycle or CS (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), chip enable (CS), UB and LB low, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode. These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1I/O8, and UB controls the higher bits, I/O9I/O16. All chip inputs and outputs are CMOS-compatible, and operation is from either a single to 3.6V supply. Device is available in the JEDEC standard 400-mL, TSOP II, and 48-ball FBGA packages.

Parameter Voltage V CC relative to VSS Voltage on any I/O pin relative to GND Power dissipation Storage temperature (plastic) Temperature with VCC applied DC output current (low) Device Symbol VtIN VtI/O PD Tstg Tbias IOUT Min Max VCC + 0.5 Unit V W

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

I/O1I/O8 I/O9I/O16 High Z High Z DOUT High Z DOUT DIN High Z High Z High Z DOUT High Z DIN
Mode Standby (ISB) Output disable (ICC) Read (ICC)
Recommended operating condition (over the operating range)

Parameter VOH Description IOH = 2.1mA Output HIGH Voltage IOH = 0.5mA IOH = 0.1mA IOL = 2.1mA VOL Output LOW Voltage IOL = 0.5mA IOL = 0.1mA VIH Input HIGH Voltage Test Conditions VCC = 2.7V VCC = 2.3V VCC = 1.65V VCC = 2.7V VCC = 2.3V VCC = 1.65V VCC = 2.7V VCC = 2.3V VCC = 1.65V VCC = 2.7V VIL IIX IOZ ICC Input LOW Voltage Input Load Current Output Load Current VCC Operating Supply Current VCC = 2.3V VCC = 1.65V GND < VIN < VCC GND VO < VCC; Outputs High CS = VIL, VIN = VIL or VIH, IOUT f=0 , VIN 0.2V or VIN > VCC 1 mS VCC = 3.6V VCC = 2.7V VCC = 2.3V VCC = 3.6V VCC = 2.7V VCC = 2.3V Min VCC + 0.5 VCC + 0.3 VCC

VCC 3.6V (55/70/100 mS) CS VIL, VIN = VIL or VCC 2.7V (55/70/100 mS) VIH, f = fMax VCC = 2.3V(55/70/100 mS) CS > VIH LB > VIH, other inputs = VIL or VIH, = 0 VCC = 3.6V VCC = 2.7V VCC = 2.3V VCC = 3.6V VCC = 2.7V VCC = 2.3V VCC = 1.2V

CS > VCC or CS Power Down Current; LB > VCC 0.2V CMOS Inputs other inputs 0V VCC, f = fMax Data Retention CS > VCC LB = VCC 0.1V f=0

Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CS, WE, OE, LB, UB I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF


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