Details, datasheet, quote on part number: AS7C1024-12TI
CategoryMemory => SRAM => Async. SRAM => 1 Mb
Description5V Fast Asynchronous, 1M, 128Kx8
CompanyAlliance Semiconductor
DatasheetDownload AS7C1024-12TI datasheet
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Features, Applications

AS7C1024 (5V version) AS7C31024 (3.3V version) Industrial and commercial temperatures Organization: 131,072 words × 8 bits High speed

12/15/20 ns address access time 7,8 ns output enable access time

Easy memory expansion with CE2, OE inputs TTL/LVTTL-compatible, three-state I/O 32-pin JEDEC standard packages

Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current AS7C1024 AS7C31024 Unit ns mA

The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) 12/15/20 ns with output enable access times (tOE) 7,8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiplebank systems. When CE1 is high CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached or ISB2). For example, the AS7C31024 is guaranteed not to exceed 0.33mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as low 2.0V. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.

Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) AS7C1024 AS7C31024 Symbol Vt2 PD Tstg Tbias IOUT Min Max +7.0 +5.0 VCC Unit °C mA

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

WE OE Data High Z High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC)

Parameter Supply voltage Device AS7C31024 AS7C1024 Input voltage AS7C31024 commercial industrial Symbol VCC VIH VIL Ambient operating temperature

|ILI| VCC = Max, VIN = GND to VCC |ILO| VCC = Max, CE1 = VIH CE2 = VIL, VOUT = GND to VCC = Max, CE1 = VIL, CE2 = VIH, f = fMax, IOUT AS7C31024 mA VCC = Max, CE1 VIH and/or AS7C1024 CE2 VIL, VIN = VIH or VIL, f = fMax, IOUT = 0mA VCC = Max, CE1 VCC­0.2V VIN GND 0.2V or VIN VCC = 0 IOL = 8 mA, VCC = Min IOH = ­4 mA, VCC = Min AS7C1024

Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals CE1, CE2, WE, OE I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF


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UL62H1708AT1K35G1 : 128K X 8 STANDARD SRAM, 35 ns, PDSO32 Specifications: Memory Category: SRAM Chip ; Density: 1049 kbits ; Number of Words: 128 k ; Bits per Word: 8 bits ; Package Type: SOP, 0.330 INCH, SOP-32 ; Pins: 32 ; Logic Family: CMOS ; Supply Voltage: 3.3V ; Access Time: 35 ns ; Operating Temperature: -40 to 125 C (-40 to 257 F)

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