Details, datasheet, quote on part number: AS7C1024-12TPC
CategoryMemory => SRAM => SRAM
DescriptionHigh Performance 128k X 8 CMOS SRAM
CompanyAlliance Semiconductor
DatasheetDownload AS7C1024-12TPC datasheet


Features, Applications

Organization: 131,072 words 8 bits High speed 10/12/15/20 ns address access time 3/3/4/5 ns output enable access time Low power consumption - Active: 660 mW max (15 ns cycle) - Standby: 55 mW max, CMOS I/O - Very low DC component in active power 2.0V data retention Equal access and cycle times Easy memory expansion with CE2, OE inputs TTL/LVTTL-compatible, three-state I/O 32-pin JEDEC standard packages - 300 mil PDIP and SOJ Socket compatible with - 400 mil PDIP and SOJ - 820 TSOP ESD protection 2000 volts Latch-up current 200 mA 3.3V and 5.0V versions available Industrial and commercial temperature available

Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current

The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memories (SRAM) organized as 131,072 words 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) 10/12/15/20 ns with output enable access times (tOE) 3/3/4/5 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory systems. When CE1 is HIGH CE2 is LOW the device enters standby mode. The standard AS7C1024 is guaranteed not to exceed 55 mW power consumption in standby mode. Both devices offer 2.0V data retention. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL/LVTTL-compatible, and operation is from a single 5V supply or 3.3V supply (AS7C31024). The AS7C1024 and AS7C31024 are packaged in common industry standard packages.

Parameter Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Temperature under bias DC output current Symbol Vt PD Tstg Tbias Iout Min Max Unit mA

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

WE OE Data High Z High Z High Z Dout Din Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable Read Write

Parameter Supply voltage AS7C1024 AS7C31024 Symbol VCC GND VIH VIL Min Nominal Max 3.6 0.0 VCC + 0.5 VCC 0.5 0.8 Unit

Parameter Input leakage current Output leakage current Operating power supply current Standby power supply current Symbol | ILI | ILO | ICC ISB ISB1 VOL VOH Test conditions VCC = Max, Vin = GND to VCC CE1 = VIH CE2 = VIL, VCC = Max, Vout = GND to VCC CE1 = VIL, CE2 = VIH, f = fmax, Iout CE1 = VIH CE2 = VIL, f = fmax CE2 0.2V,

Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals

= 1 MHz, Ta = Room temperature, VCC = 5V) Test conditions CE1, CE2, WE, = 0V I/O Vin = Vout = 0V Max 5 7 Unit pF


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