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Details, datasheet, quote on part number:P2005A
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Datasheet text preview:
PRELIMINARY Specification
Alliance Semiconductor®
P2005A/S
Low Frequency EMI Reduction IC
FEATURES · · · · · · FCC approved method of EMI attenuation Provides up to 15 dB of EMI suppression Generates a 1 X or ˝ X low EMI spread spectrum clock of the input frequency Input frequency range from 8MHz to 32MHz Internal loop filter minimizes external components and board space Frequency Deviation: P2005A: +/-1% to +/-3% P2005S: +/-0.6% to +/-1.8% The P2005X modulates the output of a single PLL in order to "spread" the bandwidth of a synthesized clock and, more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal's bandwidth is called "spread spectrum clock generation". APPLICATIONS The P2005X is targeted towards EMI management for high-speed digital applications such as PC peripheral devices, consumer electronics, and embedded controller systems. . Figure 1 - P2005X Pin Diagram · · · · · · · SSON# control pin for spread spectrum enable and disable options Low cycle-to-cycle jitter 3.3V or 5.0V operating voltage range 16 mA output drives TTL or CMOS compatible outputs Ultra-low power CMOS design Available in 8 pin SOIC and TSSOP
PRODUCT DESCRIPTION The P2005X is a versatile spread spectrum frequency modulator designed specifically for input clock frequencies from 8 MHz to 32 MHz (see Table 1). P2005X can generate an EMI reduced clock from crystal, ceramic resonator, or system clock. The P2005X offers various percentage deviations ranging from +/-0.6% to +/3.0% (see Table 2). The P2005X reduces electromagnetic interference (EMI) at the clock source, allowing a system wide EMI reduction for all the down stream clocks and data dependent signals. The P2005X allows significant system cost savings by reducing the number of circuit board layers, ferrite beads, shielding, and other passive components that are traditionally required to pass EMI regulations. The P2005X uses the most efficient and optimized modulation profile approved by the FCC and is implemented in a proprietary all-digital method.
XIN/ CLK XOUT DIV2 VSS
1 2 3 4
8 7 6 5
VDD ModOUT SSON# SR0
May, 2002 Revision E
PulseCore A Division of Alliance Semiconductor 3160 De La Cruz Blvd., Suite 200 · Santa Clara · CA · 95054 Tel (408) 748-6988 · Fax (408) 748-0009 http://www.pulsecore.com 1 of 1
PRELIMINARY Specification
Alliance Semiconductor® Figure 2 - P2005X Block Diagram
SR0 SSON# VDD DIV2
P2005A/S
Modulation XIN XOUT Feedback Divider Crystal Oscillator Frequency Divider
PLL
Phase Detector
Loop Filter
VCO
Output Divider
ModOUT
P2005 Block Diagram VSS
Input Frequency 0 (1/2X) DIV2 1 (1X)
8 MHz 4 MHz 8 MHz
Table 1 - Output Frequency Selections 12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 12 MHz 16 MHz 20 MHz 24 MHz 28 MHz
32 MHz 16 MHz 32 MHz
Output Frequenc y
P/N P2005A P2005S
Table 2 - Frequency Deviation Selections as a Function of Input Frequency Input Frequency Range SR0 8 MHz 12 MHz 16 MHz 20 MHZ 24 MHz 28 MHz 32 MHz +/-3.0% +/-2.5% +/-2.0% +/-1.8% +/-1.5% +/-1.5% +/-1.3% 0 +/-2.5% +/-2.0% +/-1.8% +/-1.5% +/-1.3% +/-1.3% +/-1.0% 1 0 1 +/-1.8% +/-1.5% +/-1.5% +/-1.2% +/-1.2% +/-1.1% +/-1.1% +/-0.9% +/-0.9% +/-0.8% +/-0.9% +/-0.8% +/-0.8% +/-0.6%
Modulation Rate (KHz) (Xin/20) * 62.5 (Xin/20) * 62.5 (Xin/20) * 62.5 (Xin/20) * 62.5
PIN DESCRIPTION PIN # 1 2 3 Name XIN/CLK XOUT DIV2 Type I I I Description Connect to crystal or clock. Crystal output Digital logic input used to select normal output mode or divide-by-2 output mode. When this pin is High, the frequency of the output clock is the same as the input clock frequency. When it is tied Low, the output frequency is half the input clock frequency. This pin has an internal pull-up resistor. Ground Connection. Connect to system ground. Digital logic input used to select Spreading Range (see Table 1). This pin has an internal pull-up resistor. Digital logic input used to enable Spread Spectrum function (Active Low). Spread Spectrum function enable when LOW, disable when HIGH. This pin has an internal pull-low resistor. Spread Spectrum Clock Output. Connect to +3.3V or 5.0V
PulseCore A Division of Alliance Semiconductor 3160 De La Cruz Blvd., Suite 200 · Santa Clara · CA · 95054 Tel (408) 748-6988 · Fax (408) 748-0009 http://www.pulsecore.com 2 of 2
4 5 6 7 8
VSS SR0 SSON# ModOUT VDD
P I I O P
May, 2002 Revision E
PRELIMINARY Specification
Alliance Semiconductor® SPREAD SPECTRUM SELECTION Table 1 and Table 2 illustrate the two possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center frequency (Note: the center frequency is the frequency of the external reference input on CLKIN, Pin 1). Example: The P2005X is designed for communications, digital video and imaging applications. It is not only optimized for operation in the 8MHz 30MHz range, but its output frequency can be extended down to one half of the input clock frequency using the Divide-by-Two feature. This feature extends low frequency operation to as low as 4MHz. Setting Pin 3 low (DIV2=0; Divide-by-Two mode) sets the output frequency (ModOUT) to half the frequency of the input clock (CLKIN). This is a simple way to generate a spread spectrum modulated low frequency clock when only a higher frequency signal is available. If you want the output frequency to be the same as the input, you can either set DIV2=1 or leave it unconnected. Selecting The P2005X's spread options is a matter of either setting SR0=1 or SR0=0. Setting SR0=1 sets a lower modulation spread, while setting it to 0 introduces a wider spectral spread in the output clock (see Table 1 and Table 2). The example in Figure 3 below shows the device set to the Divide-by-Two mode (DIV2=0) with a lower spectrum range (SR0=1). The versatility provided by allowing both clock division and spread spectrum on one chip is already proving to be a popular solution among leading system manufacturers. Figure 3 - P2005X Application Schematic
P2005A/S
8.832 MHz Crystal
1 2 3 4
CLKIN XOUT DIV2 VSS
P2005
VDD ModOUT SSON# SR0
8 7
0.1uF
6 5
+3.3V
Modulated 4.416 MHz is connected to CLK input pin of the system
May, 2002 Revision E
PulseCore A Division of Alliance Semiconductor 3160 De La Cruz Blvd., Suite 200 · Santa Clara · CA · 95054 Tel (408) 748-6988 · Fax (408) 748-0009 http://www.pulsecore.com 3 of 3
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