Datasheet text preview:
EP20K400 Device Pin-Outs ver. 1.0 Pin Name (1) MSEL0 (2) MSEL1 (2) nSTATUS (2) nCONFIG (2) DCLK (2) CONF_DONE (2) INIT_DONE (3) nCE (2) nCEO (2) nWS (4) nRS (4) nCS (4) CS (4) RDYnBSY (4) CLKUSR (4) DATA7 (4) DATA6 (4) DATA5 (4) DATA4 (4) DATA3 (4) DATA2 (4) DATA1 (4) DATA0 (2), (5) TDI (2) TDO (2) TCK (2) TMS (2) TRST (2) Dedicated Inputs Dedicated Clock Pins LOCK (6) CLK2 (7) DEV_CLRn (3) DEV_OE (3) VCCINT 652-Pin BGA U35 W35 AN17 W32 U3 AM17 C16 U1 C19 M1 N1 P2 R2 A14 C15 M6 L6 E7 B5 B7 A8 C13 U4 W1 C17 AN19 AM19 D19 B17, B19, AP17, AP19 U2, W34 AB6 U2 T6 Y5 A17, A19, D12, D24, E12, E24, F3, F35, G30, H1, H5, K31, L3, M30, N4, N35 R5, R34, U5, U34, W3, W31, W33, AA4, AA31, AC3, AC32, AE2, AE33, AG1, AH4, AH31, AH35, AK33, AL2, AL12, AL24, AM12, AM24, AR17, AR19 AL3, AL4, AL17, AL19, AL31, AL32, AM5, AN4, AN32, AN33, C4, C32, D5, D31, E3, E4, E17, E19, F30, F31, U6, U30, W6, W30, 655-Pin PGA A23 C23 AE41 C25 BA23 AC47 AE7 BE25 AC9 BF14 AY20 BB20 BD20 AH4 AH6 BG13 BB16 BC3 AR7 AV4 AP6 AH8 BE23 BG23 AE1 AC45 AD40 AD2 AB4, AC5, AC43, AE43 H24, AY24 BG29 AY24 AY22 BF26 A3, A45, B24, C1, C11, C19, C29, C37, C47, D24, G47, L3, L45, N1, N47, W3, W45, AA1, AA47, AD4, AD44, AG1, AG47, AJ3, AJ45, AR1, AR47, AU3, AU45, AY8, BA1, BA47, BD24, BE1, BE11, BE19, BE29, BE37, BE47, BG3, BG45 E9, E15, E21, E27, E33, E39, G7, G41, J5, J43, R5, R43, AA5, AA43, AG5, AG43, AN5, AN43, AW5, AW43, BA7, BA41, BC9, BC15, BC21, BC27, BC33, BC39 BD28 672-Pin FineLine BGA N21 N20 AA13 P21 N7 AA12 J15 P6 G14 P9 N10 M9 T6 J14 K14 M10 L8 F6 G9 F10 J12 K13 N6 P7 G13 AA14 AA15 F14 F13, H14, Y13, Y14 N8, P20 U6 N8 R9 R8 A3, A24, B3, B8, B19, B24, C1, C2, C25, C26, D3, D24, K11, L10, L15, M13, M16, N2, N12, P15, P16, P24, P25, R11, R14, T12, T17, U9, U16, AC3, AC24, AD1, AD2, AD25, AD26, AE3, AE8, AE19, AE24, AF3, AF24 A6, A13, A21, J10, K9, K16, L12, L17, M11, M14, N3, N15, N24, P12, R13, R16, T10, T15, U11, U18, V10, V17, AF6, AF13, AF21
VCCIO
VCC_CKLK (8)
W4
N11
Altera Corporation
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EP20K400 Device Pin-Outs ver. 1.0 Pin Name (1) GNDINT 652-Pin BGA A1, A18, A35, B1, B2, B18, B34, B35, C2, C3, C18, C33, C34, C35, D2, D3, D4, D17, D18, D32, D33, D34, E5, E6, E18, E30, E31, E32, E33, F18, V1, V2, V3, V4, V5, V6, V30, V31, V32, V33, V34, V35, AK18, AL5, AL6, AL18, AL30, AM18, AM2, AM3, AM4, AM31, AM32, AM33, AM34, AN1, AN2, AN3, AN18, AN34, AN35, AP1, AP2, AP18, AP34, AP35, AR1, AR18, AR35, 655-Pin PGA A47, B2, C13, C21, C27, C35, C45, D4, F24, J1, J47, N3, N45, R1, R47, W1, W47, AA3, AA45, AD6, AD8, AD42, AG3, AG45, AJ1, AJ47, AN1, AN47, AR3, AR45, AW1, AW47, BB24, BE3, BE13, BE21, BE27, BE35, BE45, BG1, BG47 672-Pin FineLine BGA A2, A8, A14, A19, A25, B1, B2, B6, B21, B25, B26, C3, C13, C24, D4, D23, H8, H19, J9, J18, K10, K17, L11, L13, L16, M12, M15, N1, N4, N13, N14, N25, N26, P1, P2, P3, P13, P14, P23, P26, R12, R15, T11, T16, U10, U17, V9, V18, W8, W19, AC4, AC23, AD3, AD13, AD24, AE1, AE2, AE6, AE21, AE25, AE26, AF2, AF8, AF14, AF19, AF25
GNDIO (9)
GND_CKLK (8) No Connect (N.C.)
W2
E7, E13, E19, E29, E35, E41, G5, G43, H40, N5, N43, W5, W43, AJ5, AJ43, AR5, AR43, AY40, BA5, BA43, BC7, BC13, BC19, BC29, BC35, BC41, BF46 BD26
Total User I/O Pins (10)
502
502
P11 A15, A16, B13, B14, B15, B16, C11, C12, C14, C15, C16, AD11, AD12, AD14, AD15, AD16, AE12, AE13, AE14, AE15, AF12, AF15, 502
Altera Corporation
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EP20K400 Device Pin-Outs ver. 1.0 Notes: (1) All pins that are not listed are user I/O pins. (2) This pin is a dedicated pin; it is not available as a user I/O pin. (3) This pin can be used as a user I/O pin if it is not used for its device-wide or configuration function. (4) This pin can be used as a user I/O pin after configuration. (5) This pin is tri-stated in user mode. (6) This pin shows the status of the ClockLock and ClockBoost circuitry. When the ClockLock and ClockBoost circuitry is locked to the incoming clock and generates an internal clock, LOCK is driven high. LOCK remains high if a periodic clock stops clocking. The LOCK function is optional; if the LOCK output is not used, this pin is a user I/O pin. (7) This pin drives the ClockLock and ClockBoost circuitry. (8) This pin is the power or ground for the ClockLock and ClockBoost circuitry. To ensure noise resistance, the power and ground supply to the ClockLock and ClockBoost circuitry should be isolated from the power and ground to the rest of the device. VCC_CKLK has the same voltage specifications as the VCCINT and should be connected to a 2.5-V power supply. If the ClockLock or ClockBoost circuitry is not used, this power or ground pin should be connected to VCCINT or GNDINT, respectively. (9) GNDIO and GNDINT are connected together in BGA packages. (10) The user I/O pin count includes dedicated inputs, dedicated clock inputs, and all I/O pins.
Altera Corporation
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