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Details, datasheet, quote on part number:EV2002
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| Part: | EV2002 |
| Category: | Communication => Network |
| Description: | Dual Serial Backplane Device Evaluation Board |
| Company: | AMCC (Applied Micro Circuits Corp) |
| Datasheet: | Download EV2002 datasheet File size : 151 kB |
| Request For quote: | Find where to buy EV2002
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Datasheet text preview:
Part Number EV2002 Revision 1.0 - April 13, 2000
EV2002
Dual Serial Backplane Device
Introduction
EVALUATION BOARD
The S2002 evaluation board provides a flexible platform for verifying the operation of the S2002 Dual Serial Backplane Device. This document provides information on the S2002 evaluation board's contents and layout. It should be used in conjunction with the S2002 product data sheet. Contact your local AMCC field applications engineer or regional sales manager to discuss any questions or concerns you may have.
EV2002 Kit Contents
S2002 evaluation board EV2002 device specification (This document) Two minicoax cables labeled as "Cable #1" (To loop back clock in parallel loopback configuration) Tw o minicoax cables labeled as "Cable #2" (To loop back KFLAGx, KGENx, and DNx in parallel loopback configuration)
Board Description
The top view of the S2002 evaluation board is shown in Figure 1. The high-speed differential LVPECL receive RXxP/N, and transmit TXxP/N signals (where lower case "x" is A and B for each channel) are brought in and out of the device on SMA connectors, as shown on the top and left edges of the board. The reference clock is brought in through the SMA connector labeled as REFCLK.
Figure 1. S2002 Evaluation Board
GND
TXAP
TXAN
TXBN
TXBP
REFCLK
VDD GND
RXBN
Applied Micro Circuits Corp. 6290 Sequence Dr. San Diego, CA 92121 S2002 Evaluation Board
*
RXBP
S2002
RXAN
AMCC
RCBP RCBN ERRC KFLAGB DOUTB7 DOUTB6 DOUTB5 DOUTB4 DOUTB3 DOUTB2 DOUTB1 DOUTB0 EOFB RCAP RCAN ERRA KFLAGA DOUTA7 DOUTA6 DOUTA5 DOUTA4 DOUTA3 DOUTA2 DOUTA1 DOUTA0 EOFA
I/P
GND DNB KGENB DINB7 DINB6 DINB5 DINB4 DINB3 DINB2 DINB1 DINB0 TCLKB DNA KGENA DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINA0 TCLKA TCLK0
AMCC
REFCLK(S) DINB7(S) GND O/P
RXAP
1 A
FR SW TO DUT FR DIPSWITCH
SYNC LC BYP CMODE TESTMODE
RESET
ON
ON 1234
DOUTB3 DINB2 TCLKB DINB3 DIND0 DIND2 TESTMODE1
GND
RESET LPENA LPENB MODE TMODE RATE CLKSEL
TDO TCK TMS TDI TRS
"1"
GND
1234567
"0"
*ERRB in the S2002 data sheet is labeled as "ERRC" on the S2002 evaluation board.
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EV2002 Dual Serial Backplane Device
Revision 1.0 - April 13, 2000
EVALUATION BOARD
Parallel Loopback Test Setup
Typical tests performed with the S2002 evaluation board are Bit Error Rate Testing (BERT) and jitter testing. In each case, it is easiest to configure the evaluation board for serial input and output (I/O), looping back the parallel I/O with jumpers. The serial I/O (parallel loopback) configuration is shown in Figure 2 and is described below. DIP switch settings for parallel loopback, where low = logic 0 and high = logic 1, are: Signal Name LPENA LPENB TMODE RATE CLKSEL SYNC CMODE TESTMODE DIP Switch Setting low low high high or low (determined by the desired serial data rate) high or low (determined by the desired reference clock rate) low high low
In order to configure the board for parallel loopback, the parallel input data must be clocked into the device with the TCLKx input clocks as shown in Figure 2. This clock is provided by looping the RCxP output clock back into the respective TCLKx input with one of the minicoax cables labeled as "Cable #1" that are provided in the EV2002 kit. Also, in this test configuration, the KFLAGx output must be looped back into the DNx and KGENx inputs by using the minicoax cables labeled as "Cable #2" that are provided in the EV2002 kit. These cables need only be connected for the channel(s) under test.
Figure 2. Parallel Loopback Configuration
GND
TXAP
TXAN
TXBN
TXBP
REFCLK
VDD GND
RXBN
RXBP
S2002
RXAN
AMCC
RCBP RCBN ERRC KFLAGB DOUTB7 DOUTB6 DOUTB5 DOUTB4 DOUTB3 DOUTB2 DOUTB1 DOUTB0 EOFB RCAP RCAN ERRA KFLAGA DOUTA7 DOUTA6 DOUTA5 DOUTA4 DOUTA3 DOUTA2 DOUTA1 DOUTA0 EOFA
I/P
GND
AMCC
S2002 Evaluation Board
REFCLK(S) DINB7(S) GND O/P
Cable #2
DNB KGENB DINB7 DINB6 DINB5 DINB4 DINB3 DINB2 DINB1 DINB0 TCLKB
Cable #1
Cable #2
DNA KGENA DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINA0 TCLKA TCLK0
RXAP
1 A
Cable #1
FR SW TO DUT FR DIPSWITCH
SYNC LC BYP CMODE TESTMODE
RESET
ON
ON 1234
DOUTB3 DINB2 TCLKB DINB3 DIND0 DIND2 TESTMODE1
GND
RESET LPENA LPENB MODE TMODE RATE CLKSEL
TDO TCK TMS TDI TRS
"1"
GND
1234567
"0"
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EV2002 Dual Serial Backplane Device
Revision 1.0 - April 13, 2000
EVALUATION BOARD
Electrical Connections
Power Connections A terminal post is provided on the top edge of the board for the power and ground connections to the S2002 Dual Serial Backplane Device. The S2002 voltage is specified at +3.3 V +/-5%.
Parallel I/O Header Terminals
Parallel input and output (I/O) signals are brought in and out on the connector banks on the right edge of the board. There is one connector bank for each channel (A and B). DINx[0:7] Data In. TTL input. Transmit Data for Channels A and B. Parallel data on this bus is clocked in on the rising edge of TCLKx or REFCLK. KGENx K-Character Generation. TTL input. KGENA high causes the data on DINA[0:7] to be encoded into a KCharacter. (See S2002 data sheet). DNx Data_Not. TTL input. When low, data present on DINx[0:7] is 8B/10B encoded and transmitted serially. When high, special character/sequences are generated as indicated in the S2002 data sheet. DOUTx[0:7] Data Out. TTL output. Receive Data Outputs for Channels A and B. Parallel data on this bus is valid on the rising edge of RCxP in full clock mode, and valid on the rising edge of both RCxP and RCxN in half clock mode. KFLAGx K-Character Flag. TTL output. A high on KFLAGx indicates that a valid control character has been detected. ERRx Receive Error. TTL output. A high on ERRx indicates the occurrence of either a parity error or an invalid codeword error during decoding of the received data. TCLKx Transmit Clock. TTL input. When TMODE is high, this signal is used to clock data on DINx[0:7], DNx, and KGENx into the S2002. When TMODE is low, TCLKx is ignored. TCLKO Transmit Clock Out. TTL output. TTL Output Clock at the parallel data rate. This clock is provided for use by upstream circuitry. RCxP/N Receive Clock. TTL output. Parallel receive data, DOUTx[0:7], KFLAGx, ERRx, and EOFx are valid on the rising edge of RCxP when in full clock mode, and valid on the rising edge of both RCxP and RCxN in half clock mode. EOFx End of Frame Detect. TTL output. A high on EOFx indicates that a valid K28.5 has been detected and is present on the parallel data outputs DOUTx[0:7]. TDO Test Data Out. TTL output (tristate). JTAG data output. Can be high impedance under JTAG controller command. TCK Test Clock. TTL input. JTAG test clock. TMS Test Mode Select. TTL input. Enables JTAG testing of device. TDI Test Data In. TTL input. JTAG data input. TRS Test Reset. TTL input. Resets JTAG test state machine. FR SW Provided with a jumper to TO DUT to enable the push-button RESET on the evaluation board. TO DUT Provided with a jumper to FR SW to enable the push-button RESET on the evaluation board. FR DIPSWITCH Not used for this device. REFCLK(S), DNB7(S) Not used for this device. DOUTB3, DINB2, TCLKB, DINB3, DIND0, DIND2 Not used for this device. TESTMODE1 Test Mode Control. Provided with a jumper to logic 0 for normal operation.
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EV2002 Dual Serial Backplane Device
Revision 1.0 - April 13, 2000
EVALUATION BOARD
SMA Connectors
RXxP/N Receive Serial Data for Channels A or B. Differential LVPECL inputs. TXxP/N Transmit Serial Data for Channels A or B. Differential LVPECL outputs. REFCLK Reference Clock. TTL input. Clock used for the transmit VCO and frequency check for the clock recovered from the receiver serial data.
DIP Switches
The S2002 evaluation board is provided with DIP switches at the bottom of the board to control the static functions of the on-board device. DIP switch settings are outlined in Table 1. Moving the switch to the "ON" position creates a logic 1 (high), moving it away from the "ON" setting creates a logic 0 (low).
Table 1. DIP Switch Settings
DIP Name RESET LPENA LPENB MODE TMODE Description Not used for this device. Use push-button RESET instead. Loopback Enable Channel A. When low, the device performs normal transceiver operation. When high the serial output for each channel is looped back to its input. Loopback Enable Channel B. When low, the device performs normal transceiver operation. When high the serial output for each channel is looped back to its input. Not used for this device. Transfer Mode Control. When TMODE is low, REFCLK is used to clock data on DINx[0:7], DNx, SYNC, and KGENx into the S2002. When TMODE is high, TCLKx is used to clock data into the S2002. When low the S2002 operates with the serial output rate equal to the VCO frequency. When high the S2002 operates with the VCO internally divided by 2 for all functions. REFCLK Select input. This signal configures the PLL for the appropriate REFCLK frequency. When CLKSEL = 0, the REFCLK frequency equals the parallel data rate. When CLKSEL = 1, the REFCLK frequency is half the parallel data rate (and is internally x2 multiplied). When high, used to generate a special sequence of K28.5 characters. Not used for this device. Clock Mode Control. When low, the rate of the parallel output clock (RCxP/N) is half the data rate. When high, the rate of the parallel output clock (RCxP/N) is equal to the data rate. Test Mode Control. Low for normal operation.
RATE CLKSEL
SYNC LC BYP CMODE
TESTMODE
Schematic and Bill of Materials
The S2002 evaluation board schematic is shown in Figure 3. The power and ground connections for the S2002 evaluation board are shown in Figure 4. The bill of materials for the S2002 evaluation board is provided in Tables 2 and 3.
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EV2002 Dual Serial Backplane Device
Revision 1.0 - April 13, 2000
EVALUATION BOARD
Figure 3. S2002 Evaluation Board Schematic
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