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Details, datasheet, quote on part number:EV2060QF
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Datasheet text preview:
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REVISION 4.0 REVISION 4.0
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
EV2060 EV2060
EVALUATION BOARD OVERVIEW
This document describes operation and usage of the S2060 evaluation boards. The evaluation boards allow users to become familiar with the functionality of the S2060 Gigabit Ethernet Transceiver. Specifically, Bit Error Rate (BER), jitter, and basic performance can be tested using the evaluation boards. This document provides a complete board description, explains various test configurations, and contains a bill of materials with a corresponding schematic. This document should be used in conjunction with the S2060 data sheet and application note. Figure 1 shows an outline of the S2060A evaluation board.
Figure 1. S2060 Evaluation Board
C D
A
D
D
A
A
A
A
GND
B
May 9, 2000
1
REVISION 4.0
EV2060
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
EVALUATION BOARD DESCRIPTION
This section describes the functionality of the connectors and settings recommended for the S2060 evaluation boards. Brief descriptions of the SMA connectors on board, dip switch descriptions and settings, power and grounds, output levels, header settings, and probes are presented. The letters "A", "B", "C", and "D" correspond to specific parts on the evaluation board shown in Figure 1, and are described in the following section according to their letter designation in Figure 1.
[A] SMA Connectors
SMA connectors are provided for the differential serial data input/output signals and output clock. Additional SMA connectors are provided for an optional differential serial input clock, the external TTL reference clock and the optional external parallel input clock. Table 1 gives a description of the SMA connectors.
Table 1. SMA Connectors
Connectors Receive Serial Data (RXP/RXN) Transmit Serial Data Output (TXP/TXN) Reference Clock (REFCLK) Description Differential inputs. Serial data inputs of the S2060 Differential outputs. Serial data output data. Reference clocking.
[B] Dip Switches
The evaluation board is equipped with a DIP switch to control the static control functions of the on-board devices. For both arrays the OFF (open = "0") condition of the DIP switch asserts a logic low on the assigned signal, and the ON (closed = "1") condition asserts a logic high. Note that "0" and "1" are printed on the evaluation board. Table 2 shows the functional DIP switch descriptions. Table 3 shows DIP switch settings corresponding to the tests described at the end of this document.
Table 2. Dip Switch Functional Description
Dip Name RATEN
Description Rate Select. Active Low. This signal configures the PLL's for the appropriate TBC frequency. When inactive, the operating range is 625 MHz. When active, the operating range is 1.25 GHz. Enable Wrap. Active High. When active, the transmitter serial data outputs are internally routed to the receiver serial data inputs. TXP/N are static (logic 1) in this state. When inactive, the RXP/N serial inputs are selected (normal operation). Enable Comma Detect. Active High. When active, enables detection of the comma sync pattern to set the word frame boundary for the data to follow. When inactive, data is treated as unframed. Lock to Reference Input. Active Low. When inactive or open, the receive PLL will lock to the incoming data (normal operation). When active, the receive PLL is forced to lock to the TBC input.
EWRAP
EN_CDET
-LCK_REF
2
May 9, 2000
REVISION 4.0
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
Table 3. Dip Switch Settings for Test and Evaluation Configurations
(Not Labeled) BER TEST JITTER TEST 0 0 RATEN 1 1 EWRAP 0 0 EN_CDET 0 0 -LCK_REF 1 1
EV2060
[C] Power/Ground
Three terminal outputs are provided at the top edge of the board for Vcc and Vee. The S2060 is specified for 3.3 V +/- 5%.
Table 4. S2060 Power and Ground Values
Vcc Terminal Post 3.3 V 2.0 V Vee Terminal Post 2.0 V 1.3 V LVPECL Output Termination 150 to Vee 50 to Vcc 2.0 V (GND)
Figure 2. Single-Ended LVPECL Output Swing
VOH Vcc -1.3 V (internal DC bias point) VOL Termination = 50 to (VCC-2V) or 150 to VEE
The TXP/N single-ended LVPECL output swing is shown in Figure 2. The bias point is internally set 1.3 volts below the Vcc rail. As discussed in both the S2060 data sheet and application note, 150 pulldown resistors are recommended on the positive and negative outputs for full output voltage swing. Test equipment inputs, however, typically provide 50 loads. When interfacing to test equipment the Vcc and Vee input levels may be shifted to 2.0 V and 1.3 V respectively in order to maintain full voltage swing with the smaller load. Table 4 summarizes the voltage rail settings and associated output loading.
May 9, 2000
3
REVISION 4.0
EV2060
[D] Probes (Headers)
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
RCB1, RCB0, and COM_DET are probe points. The output levels of RCB1, RCB0, and COM_DET pins can be probed during testing. These pins must be left unjumpered. RX[0:9], TX[0:9] and GND can be either jumpered, utilized as probe points, or utilized as active I/O. RX[0:9] and TX[0:9] can be jumpered such that parallel output (RX[0:9] ) is bridged directly to the parallel input (TX[0:9]). Selected RX[0:9] and TX[0:9] pins can also be jumpered to ground to set up a static input configuration. The probe descriptions are given in Table 5. DUT input and output signals are typically routed to and from the evaluation board through the serial I/O. Providing evaluation board I/O through the parallel connectors would require the user to construct a cable harness.
Table 5. Evaluation Board Header Descriptions
Header RBC1 RBC0
Description Complementary Receive Byte Clocks. In full rate mode, parallel receive data is valid on the rising edges of RBC0 and RBC1. For half rate, output data is valid on the rising edge of RBC1. Comma Detect. Active High. When EN_CDET is active, COM_DET indicates that the sync character is present on the parallel bus bits RX[0:9]. Upon detection of the comma sync character (0011111xxx, positive polarity) this output data is valid on the rising edge of RBC1 and remains high for one RBC1 clock period. When EN_CDET is inactive, COM_DET is held low (logic 0). Upon change of state of the EN_CDET input, the COM_DET output response will be delayed by a maximum of 3 byte times. Receive Data Outputs. For full rate output, parallel data on this bus is valid on the rising edges of RBC0 and RBC1. RX[0] is the first bit received. Transmit Data. Parallel data on this bus is clocked in n the rising edge of TBC. TX[0] is transmitted first. Ground.
COM_DET
RX[0:9] TX[0:9] GND
4
May 9, 2000
REVISION 4.0
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS SCHEMATIC/BILL OF MATERIALS
EV2060
Figures 3 and 4 provide a schematic representation of the evaluation boards. Table 6 lists the Bill of Materials for the evaluation boards.
Figure 3. Signal Connections
C1
SMA
C1
SMA
RXP
C1 R2 C1
TXP
RXN
TXN
R3 R3
RBC0 REFCLKP
R1
S2060
RBC1 COM-DET
RX0
TX0
EN_CDET
LCK_REF
EWRAP
RATEN
RX9
TX9
R4
R2
Figure 4. Power and Ground Connections
Vcc
Power Terminal (1x2)
5
C3 C1 C2
21 21
10 20
C1
C2
S2060
25 32
23
C1 C2
47 56
37
C1 C2
42 55
58 64
C1
C2
L
15 60
C1 C2
L
51
L
18
L
50
C1 C2 C1 C2
May 9, 2000
5
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