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Details, datasheet, quote on part number:EV3024
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SONET/SDH/ATM OC-12 CLOCK AND DATA RECOVERY EVALUATION BOARD SONET/SDH/ATM OC-12 CLOCK AND DATA RECOVERY EVALUATION BOARD DESCRIPTION
EV3024 EV3024
The S3024 evaluation board provides a flexible platform for verifying the operation of the S3024 clock and data recovery interface circuit. This document provides information on the board contents. It should be used in conjunction with the S3024 data sheet, which contains full technical details on the chips operation. Figure 1 shows the outline of the S3024 evaluation board. Figure 2 shows the block diagram of how the S3024 evaluation board should be connected to test equipment for Bit Error Rate (BER) testing.
Figure 1. S3024 Evaluation Board Top View
GND LOCKDET GND DUT DUT GND VCC VEE SERDATIP
SERDATIN
AMCC
S3024
SERDATOP 6290 SEQUENCE DR. SAN DIEGO, CA 92121
APPLIED MICRO CIRCUITS CORPORATION S3024 SONET/SDH/ATM OC-3/12 CRU SERDATON
GND
SERCLKOP
1
2
3
FROM DIPSW
SERCLKON GND "1" "0"
TTLREF
EXT. VEE(OSC)
LVTTL XTAL OSCLLATOR
BYPASS
DUT VEE
SD LCKREFN MODE Tied together for formal operation of LVTTL osc.
Note 1. Demo board is set up for a crystal oscillator with a "0" jumper between 2 and 3. When TTLREF is to be used, a "0" jumper should be placed between 1 to 2, and the jumper between 2 and 3 should be removed.
TO DUT
NOTE 1
GND
November 19, 1999
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EV3024
SONET/SDH/ATM OC-12 CLOCK AND DATA RECOVERY EVALUATION BOARD
Figure 2 depicts how the S3024 evaluation board can be connected for BER or jitter measurements, and shows all of the DIP switch settings. In addition, it shows the low voltage ECL (LVECL) power supply requirements for use with test equipment that utilizes 50 to (-2V) input termination. In this configuration the S3024 is configured for use with the internal S3024 Clock Recovery Unit (CRU), using a 19.44 MHz reference and operating at STS12.
Figure 2. S3024 BER Test Setup
POWER SUPPLY GND = 0V DUTVCC = 0V DUTVEE = -3.3V BYPASS = "0" SD = "1" LCKREFN = "1" MODE = "1"
S3024 BER TEST
BERT TX TEKTRONIX GIGABERT 700 or EQUIVALENT
BERT RX TEKTRONIX GIGABERT 700 or EQUIVALENT
(INPUT TERMINATION SET TO (-2V))
DATA/OUT_N
DATA/OUT_P
DATA/IN_N
DATA/IN_P
CLK/OUT_N
CLK/OUT_P
CLK/IN_N
CLK/IN_P
TEKTRONIX SJ 300 THRU_DATA REF_CLK DATA_OUT CLK_IN CLK_OUT SERDATOP -3.3V SERDATON SERDATIP DATA_P DATA_IN DATA_N SERDATIN SERCLKON SERCLKOP
(for BER)
(for jitter)
DUTVCC DUTVEE
S3024
SINGLE ENDED INPUT TO DIFFERENTIAL OUTPUT BUFFER
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November 19, 1999
SONET/SDH/ATM OC-12 CLOCK AND DATA RECOVERY EVALUATION BOARD ELECTRICAL CONNECTIONS
Power Connections
EV3024
Terminal posts are provided at the top edge of the board for VCC and VEE. The S3024 evaluation board can be configured with ECL, PECL and level shifted (LSECL) I/O so that the board can be configured to operate with different types of standard test equipment. Figures 3 through 5 demonstrate the different types of input and output waveforms that the S3024 evaluation board can output with the different voltage settings of VCC and VEE per Table 1. Note that the TTL I/O's voltage level will change to non-standard levels when the S3024 evaluation board is powered in the LSECL or LVECL power supply modes. The external test equipment environment or other standard ECL and/or +3.3V referenced ECL systems can interface to the S3024 evaluation board. The board as shown by Figures 1 and 2 can be powered to allow easy connection to the 50 to (-2V) standard ECL I/O of serial Bit Error Rate Testers (BERT) and jitter analyzers (Note: not all test equipment is 50 to (-2V) termination compatible). Table 1 illustrates the nominal input voltages for DUT VCC and VEE voltage levels shown in Figures 3 through 5. Figures 3 and 4 show that the voltages track with VEE, and Figure 5 show that the voltages track with VCC.
SMA Connectors
SMA connectors are provided for the differential serial data input/output signals and output clock. The additional SMA connector provides for an optional TTL reference clock. Receive Serial Data [SERDATIP/N] -- Differential LVPECL inputs. Serial data inputs of the S3024. Serial Data Output [SERDATOP/N] -- Differential LVPECL outputs. Serial data outputs of the S3024. Serial Clock Output [SERCLKOP/N] -- Differential LVPECL outputs. Serial recovered clock output of the S3024 TTL Reference Clock [TTLREF] -- LVTTL input. These inputs must be provided with a 19.44 MHz LVTTL crystal oscillator.
DIP SWITCHES
The evaluation board is equipped with a DIP switch, to control the static control functions of the on-board device. The OFF (open = "0") condition of the DIP switch asserts a logic low on the assigned signal, and the ON (closed = "1") condition asserts a logic high. Figure 2 shows the particular DIP switch settings that are needed for a particular test case.
Table 1. Power Connections for DUT and Test Equipment Interface
Power Supply DUT VCC DUT VEE DUT VCC DUT VEE DUT VCC DUT VEE Nominal Input Voltage +3.3V 0V 0V -3.3V +2V -1.3V Type of Signal ECL Output Termination 50 to VCC -2V 50 to -2V 50 to GND
LVPECL
LVECL
LSECL
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EV3024
SONET/SDH/ATM OC-12 CLOCK AND DATA RECOVERY EVALUATION BOARD
Figure 3. LVECL Signal Waveform
LVECL VCC = 0V -0.8V -1.3V -1.8V VEE = -3.3V +/- 5% Termination = 50 Ohms to -2V
Figure 4. LSECL Signal Waveform
LSECL VCC = +2V +1.2V +0.7V +0.2V VEE = -1.3V +/- 5% Termination = 50 Ohms to GND
Figure 5. LVPECL Signal Waveform
LVPECL VCC = +3.3V +/- 5% 2.5V 2V 1.5V VEE = 0V Termination = 50 Ohms to (VCC -2V)
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November 19, 1999
EV3024
SONET/SDH/ATM OC-12 CLOCK AND DATA RECOVERY EVALUATION BOARD
AVCC1
AVCC2
L1
VCC
L2
C1
4 3 2 1
J8
C2
VEE
C10
C14
C12
C13
C11
C15
C16
C17
C18 C19
C8 C9
C1
J1
S3024 AVCC1
AVCC SERDATIP SERDATIN AGND 5 6 7 LOCKDET MODE TTLREF 8 LCKREFN 2 3 1
JP2
AVCC AGND CAP1 CAP2 BYPASS SD 20 19 18 17 16 15
C2
AVCC2 VEE
R1 J2
LOCKDET MODE VEE
4
R6 R7
BYPASS SD
SERDATOP SERDATON 14 13
C7
J3
LCKREFN
J7 R2 R4 R5 R3
VEE VCC
9 10
DGND DVCC
SERCLKOP SERCLKON
12 11
J4
U1
J5
J6
LCKREFN BYPASS MODE
Figure 6. S3024 Evaluation Board Schematic
VCC
C3 GND XTALOSC C5
VEE
C1
C4
4 VCC OUTP 3 1 NC 2 VEE
SD
U2
GND
U6
C6 GND
5 4 3 2 1
10k U5
JP1
C2
LOCKDET
C1
JP3
2
4
6
C2
U3 VCC
8
VEE
R8
VEE
U4
1 2 3 4 5
4pswitch
1 3 5 7
1k
November 19, 1999
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