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Details, datasheet, quote on part number:EV3026
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Part Number EV3026 October 19, 1999
EV3026
SONET/SDH Clock Recovery Unit
Description
The S3026 evaluation board provides a flexible platf o r m for verifying the operation of the S3026 Clock Recovery Unit (CRU). This document provides information on the board contents and layout. It should be used in conjunction with the S3026 data sheet, which contains full technical details on the chips operation.
EVALUATION BOARD
The S3026 board is factory configured as "option B" allowing control of the operating speed via the MODE signal (SW2) and providing a test point to monitor the L O C K D E T output. Option B allows operation of the S3026 with either an on-board TTL crystal oscillator or with an external oscillator connected via the external TTL REFCLK I/Px connector.
Figure 1. Evaluation Board Layout Top View
APPLIED MICRO CIRCUITS CORP. GND DUT I/P 6290 SEQUENCE DRIVE VTT VCC SAN DIEGO, CA 92121 S3025/26/27 SONET/SDH CLOCK RECOVERY UNIT
AMCC
BUFFERED INPUT
O/P GND BUF BUF VTT VEE VCC
SERDATOP BUFFERED OUTPUTS SERDATON
SERDATIP
AMCC S3026
SERDATIN XTAL
CRU OUTPUTS
SERCLKOP
SERCLKON LOCKDETx GND DIPSWITCH OPTIONS OPT S W 2 SW3 A SQUELCHN SD Bx MODE SDN
LCKREFN SW2 SW3 BYPASS "0" "1" "0" "1"
TTL XTAL OSCILLATORx
EXTERNAL TTL REFCLK I/Px
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EV3026 SONET/SDH Clock Recovery Unit
October 19, 1999
EVALUATION BOARD
Electrical Connections
Power Connections Te r m i n a l posts are provided at the top edge of the board allowing separate control of voltage levels for the input signal termination, the S3026 itself, and 1 the S3026 output terminations. The buffers translate between the external test equipment environment or other standard ECL and/or +5V referenced ECL systems to supply the correct +5V referenced ECL to the device. The separately powered output buffers allow easy connection to the 50 to ground inputs of high performance oscilloscopes and spectrum analyzers as well as the standard ECL I/O of serial Bit Error Rate Testers (BERT) and jitter analyzers. Table 1 illustrates the nominal input voltages for IP V T T, DUT VCC and O/P VTT. The options for BUF VEE and BUF VCC are paired vertically.
These are the recommended outputs for connection of the evaluation board to monitoring instrumentation. Serial Clock Out [SERCLKOP/N] - Buffered Differential PECL outputs. The recovered serial clock, with the rising edge of SERCLKOP centered in the SERDATOP/ N bit period. The buffered outputs can drive PECL, ECL, or ground terminated instrument inputs. Driven i n p u t s must provide a 50 DC termination to the respective reference. These are the recommended outp u t s for connection of the evaluation board to monitoring instrumentation. N o t e : Accurate measurement also requires the removal of on-board zero jumpers for correct impedance matching to external 50 cabling and instrumentation. Please consult AMCC for appropriate in-factory reconfiguration. E x t e r n a l TTL Reference Clock [EXTERNAL TTL REFCLK I/Px] - TTL input providing access to the TLL Reference Clock (TTLREF) input of the S3026. This input allows operation at other than the two available S O N E T / S D H data rates. The provided TTL crystal oscillator must be removed if use of an external reference is desired. This connector can also be used to monitor the provided TTL oscillator output. Lock Detect [LOCKDET] - PECL output (Test Point). In addition to AMS connectors, the LOCKDET output is available on a test pin post for monitoring with a high impedance DVM or scope probe.
Table 1. Power Connections for DUT and Test Equipment Interface
Power Supply I/P VTT DUT VCC GND O/P VTT BUF VEE BUF VCC Nominal Input Voltage 0V / -2.0V / +3V 5.0V 0.0V DUT VCC -2V -3.0V / 0.0V / -5.0V 2.0V / 5.0V / 0.0V
DIP Switch
T h e four element DIP switch allows control of the static inputs of the S3026. The OFF (open = 1) condit i o n of the DIP switch asserts a logic high on the assigned signal, and the ON condition asserts a logic low. In option B, SW2 controls the MODE input. OFF allows operation at 622.08 Mbit/s, ON selects 155.52 Mbit/s. SW3 of the DIP switch controls the PECL SDN input. O N allows the S3026 to recover the clock from the serial data stream. OFF will force the S3026 to lock to t h e reference clock. LCKREFN when ON will also f o r c e the S3026 to lock to the reference clock. BYPASS should be ON for normal operation.
SMA Connectors Six coaxial SMA connectors are provided for the differential serial data input/output signals and output clock. A n additional SMA connector is provided for an optional external reference clock. (See Figure 1 for locations.) Serial Data In [SERDATIP/N] - Buffered Differential AC coupled PECL inputs. The clock is recovered from the transitions on these inputs. On-board termination of 50 to I/P VTT is provided, allowing proper termin a t i o n of PECL, ECL, or ground terminated data sources. Serial Data Out [SERDATOP/N] - Buffered Differential PECL outputs. The delayed version of the input serial data retimed by the recovered serial clock. The buffered outputs can drive PECL, ECL, or ground terminated instrument inputs. Driven inputs must provide a 50 DC termination to the respective reference.
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EV3026 SONET/SDH Clock Recovery Unit
October 19, 1999
EVALUATION BOARD
Figure 2. S3026 Evaluation Board Schematic
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EV3026 SONET/SDH Clock Recovery Unit
October 19, 1999
EVALUATION BOARD
Table 2. EV3026 Bill of Materials
Count 3 Component Name CC0402 Pattern 0402 Value 0.1 µF Ref Des C12 C15 C22 3 CC0604 0603 0.1 µF C14 C16 C23 5 CC0604 0603 10 µF C1 C2 C3 C4 C5 5 CC0805 0805 0.1 µF C7 C10 C18 C20 C24 3 CC0805 0805 1 µF C9 C13 C19 1 5 CC0805 CC0805 0805 0805 10 µF 100 pF C6 C8 C11 C17 C21 C25 1 1 1 1 2 CONN1X4PWR CRYSTAL DIP4 IND JP1X2 1206 JP1X2 CONN1X4PWR not used dip4 f.b. J2 X1 SW1 L1 JP1 JP2
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EV3026 SONET/SDH Clock Recovery Unit
October 19, 1999
EVALUATION BOARD
Table 2. EV3026 Bill of Materials
Count 3 Component Name MC100EL16 Pattern SO8 Value Ref Des U2 U3 U4 1 1 2 OSCTTL PWRCONX3 RC0603 0603 OSC 19.44 MHz pwrx3 1 k 1 J1 R22 R23 2 RC0603 0603 50 R24 R25 2 RC0603 0603 51 R13 R14 2 RC0603 0603 330 R11 R12 3 RC0805 0805 0 R15 R16 R21 2 RC0805 0805 0 R1 R27 1 4 RC0805 RC0805 0805 0805 0 1 k R3 R5 R6 R9 R10 1 2 RC0805 RC0805 0805 0805 2 k 50 R28 R17 R18 1 2 RC0805 RC0805 0805 0805 51 (opt) 82 R26 R4 R7 3 RC0805 0805 100 R2 R8
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