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Details, datasheet, quote on part number:EV3031B
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E4/STM-1/OC-3 ATM EVALUATION BOARD E4/STM-1/OC-3 ATM EVALUATION BOARD DESCRIPTION
EV3031B EV3031B
The S3031B Evaluation Board provides a flexible platform for verifying the operation of the S3031B transceiver interface circuit. This data sheet provides information on board contents. It should be used in conjunction with the S3031B data sheet, which contains full technical details on chip operation. Figure 1 shows the outline of the S3031B Evaluation Board and Figure 2 shows the block diagram of how the S3031B Evaluation Board should be connected to test equipment for BER testing. In this configuration the S3031B is configured for use with the internal S3031B Clock Recovery Unit (CRU), using a 19.44 MHz or 38.88 MHz reference and operating at STS-3.
Figure 1. Evaluation Board Top View
RINVTT TINVTT
DGND
AGND
AVCC
DGND
DVCC
AGND4
DVCC
+V
-V
AGND3
RSDATIN
TSDATIN
XFMR AGND1 TSDATIP RXCABI TESTCLK
RSDATIP
AGND2
RSDATON
TSDATON
AMCC
TXRSTB
RSDATOP
E4/STM-1/ OC-3
TREFCLKOUT
XFRMSTATB
XFRMSTATA
S3031B
1
TSDATOP
RSCLKON
LCV LOSOUT (LED) RXRSTB
TSCLKON
RSCLKOP XFMR TXMONO
LOSOPT REFSEL LLEB DLEB SERDSEL EQUALSEL
ON OFF ON OFF
TSCLKOP XFMR RXCBLO
TSTCLKEN DLCV CMISEL XFRMENB XFRMENA SERDATEN
REFCLK
5 4 3 2 1 SWITCH1
5 4 3 2 1 SWITCH2
LVTTL XTAL OSCILATOR
4 x 5 Pin Header
POCLK POUT0 POUT1 POUT2 POUT3
PIN0 PIN1 PIN2 PIN3
October 26, 1999
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EV3031B
E4/STM-1/OC-3 ATM EVALUATION BOARD
Figure 2 depicts how the S3031B Evaluation board can be connected for BER measurements, and shows all of the DIP switch settings and the level shifted ECL (LSECL) power supply requirements for use with test equipment that utilizes 50 to ground termination.
Figure 2. BER Test Setup
S3031B RECEIVER BER TEST SETUP
BERT RX TEKTRONIX 700 ANALYZER
SWITCH SETTINGS EQUALSEL(OPTICAL INPUT) SERDSEL DLEB LLEB REFSEL LOSOPT SERDATEN XFRMENA XFRMENB CMISEL DLCV TSTCLKEN '0' ('1' for cable input) '1' '0' '0' '1' ('0' for 38.8MHz Refclk) '1' '0' '0' '0' '0' '0' ('1' for CMI mode) '0'
DATA DATA
CLOCK CLOCK
RSCLKOP RSCLKON RSDATOP RSDATON RXCABI
(Needed to test CMI decoding of RXCABI data)
TSCLKOP TSCLKON TSDATOP TSDATON TSDATIP TSDATIN
RXCBLO RSDATIN RSDATIP
WG SF-60 PDH/SDH ERROR AND JITTER ANALYZER DATA (CMI ENCODED) CLOCK(155MHz)
S3031B DEMO BOARD
REFCLK BIAS FOR LSECL
DVCC(+5V) DVCC(+5V) +V(+2V) DGND(0V) -V(-3V) DGND(0V) TINVTT(0V) RINVTT(0V) AVCC(+5V) AGND(0V)
BERT TX
TEKTRONIX 700 GENERATOR
HP8133A
EXT INPUT (155MHz)
EXT INPUT CLOCK CLOCK DATA DATA
TRIGGER OUT CLOCK/8
19MHz
2
October 26, 1999
ON BOARD POWER TERMINAL
J30 1 2 3 4 5 6 7 8 9 10
E4/STM-1/OC-3 ATM EVALUATION BOARD
EV3031B
Figure 3 depicts how the S3031B receiver section of the evaluation board can be connected for BER measurements and jitter testing, and shows all of the DIP switch settings and the power supply requirements for use with test equipment that utilizes 50 to -2V termination.
Figure 3. Receiver BER and Jitter Test Setup
S3031B RX EYE OPENING TEST SETUP
BIAS FOR LSECL
DVCC(+5V) DVCC(+5V) +V(0V) DGND(0V) -V(-5V) DGND(0V) TINVTT(-2V) RINVTT(-2V) AVCC(+5V) AGND(0V) 1 2 3 4 5 6 7 8 9 10
ON BOARD POWER TERMINAL
BERT TX(155.52 MHz)
2^7-1 PRBS DATA PATTERN
DATA DATA CLOCK
S3031B EVALUATION BOARD
RSDATIN
SCOPE
RSDATIP RSDATON TRIGGER RSDATOP RSCLKON
CASCADE MICROTECH ECL TERMINATOR VTT= -2.45V
MEASURE DATA EYE RSCLKOP
2^7-1 PRBS DATA PATTERN
DATA CLOCK CLOCK SWITCH 1 SWITCH 2 SERDATEN '0' XFRMENA '0' XFRMENB '0' CMISEL '0' DLCV '0' TSTCLKEN '0'
DIPSWITCH SETTINGS
BERT RX (155.52 MHz)
EQUALSEL(OPTICAL INPUT) '0' SERDSEL '1' DLEB '0' LLEB '0' REFSEL '1' LOSOPT '1'
October 26, 1999
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EV3031B
E4/STM-1/OC-3 ATM EVALUATION BOARD
Figure 4 depicts how the S3031B Transmitter section of the Evaluation board can be connected for BER measurements and Jitter testing, and shows all of the DIP switch settings and the power supply requirements for use with test equipment that utilizes 50 to ground termination.
Figure 4. Transmitter BER and Jitter Test Setup
S3031B TX EYE OPENING TEST SETUP
BIAS FOR LSECL
DVCC(+5V) DVCC(+5V) +V(0V) DGND(0V) -V(-5V) DGND(0V) TINVTT(-2V) RINVTT(-2V) AVCC(+5V) AGND(0V) 1 2 3 4 5 6 7 8 9 10
BERT TX(155.52 MHz)
2^7-1 PRBS DATA PATTERN
DATA DATA CLOCK
S3031B EVALUATION BOARD
TSDATIN
SCOPE
TSDATIP TSDATON TRIGGER TSDATOP TSCLKON
CASCADE MICROTECH ECL TERMINATOR VTT= -2.45V
MEASURE DATA EYE TSCLKOP
2^7-1 PRBS DATA PATTERN
DATA CLOCK CLOCK
DIPSWITCH SETTINGS
SWITCH 1 EQUALSEL(OPTICAL INPUT) '0' SERDSEL '1' DLEB '0' LLEB '0' REFSEL '1' LOSOPT '1' SWITCH 2 SERDATEN '0' XFRMENA '0' XFRMENB '0' CMISEL '0' DLCV '0' TSTCLKEN '0'
BERT RX (155.52 MHz)
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October 26, 1999
ON BOARD POWER TERMINAL
E4/STM-1/OC-3 ATM EVALUATION BOARD ELECTRICAL CONNECTIONS
Power Connections
EV3031B
Terminal posts are provided at the top edge of the board for VCC and VEE. The S3031B Evaluation Board can be configured with ECL, PECL and level shifted (LSECL) I/O so that the board can be configured to operate with different types of standard test equipment. Figures 5 through 7 demonstrate the different types of input and output waveforms that the S3031B Evaluation Board can output with the different voltage settings of VCC and VEE as per Table 1. Note that the TTL I/O's voltage level will change to non-standard levels when the S3031B Evaluation Board is powered by the different voltage.
Figure 5.
LVECL VCC = 0V -0.8V -1.3V -1.8V VEE = -5V +/- 5% Termination = 50 to -2V
Figure 6.
LSECL VCC = +2V +1.2V +0.7V +0.2V VEE = -3V +/- 5% Termination = 50 to GND
October 26, 1999
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