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Details, datasheet, quote on part number:EV3032
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SONET/SDH/ATM OC-12 TRANSCEIVER EVALUATION BOARD SONET/SDH/ATM OC-12 TRANSCEIVER EVALUATION BOARD
Description
EV3032 EV3032
The S3032 evaluation board provides a flexible platform for verifying the operation of the S3032 transceiver interface circuit. This document provides information on the board contents. It should be used in conjunction with the S3032 data sheet, which contains full technical details on the chips operation. Figure 1 shows the outline of the S3032 evaluation board. Figure 2 shows the block diagram of how the S3032 evaluation board should be connected to test equipment for Bit Error Rate (BER) testing. Figure 3 shows the test setup for the BER measurements and jitter testing.
Figure 1. S3032 Evaluation Board Top View
DUT VEE TSDP
GND
DUT VCC
REFCLKP
REFCLKN
TTLREF
APPLIED MICRO CIRCUITS CORPORATION S3032 SONET/SDH/ATM 0C-3/12 TRANSCEIVER WITH CDR
POCLK PCLK TSDN PICLK PIN7 PIN6 PIN5 PIN4
AMCC
6290 SEQUENCE DR. SAN DIEGO, CA 92121
S3032
TSCLKN
PIN3 PIN2 PIN1 PIN0 GND
GND POUT7:0 PIN7:0 GND
TSCLKP
FOR NC
OPEN
(MODE JUMPERS)
FP GND
SLPTIME
SDPECL
TESTEN
MODE1
GND "1"
MODE0
DLEB
LLEB
OOF
RSDP
RSDN
"1" RSTB
"0"
"0"
September 22, 1999
1
SONET/SDH/ATM OC-12 TRANSCEIVER EVALUATION BOARD
EV3032
Figure 2 depicts how the S3032 evaluation board can be connected for BER measurements, and shows all of the DIP switch settings and the Level Shifted ECL (LSECL) power supply requirements for use with test equipment that utilizes 50 to ground termination. In this configuration the S3032 is configured for use with the internal S3032 Clock Recovery Unit (CRU), using a 19.44 MHz reference and operating at STS-12.
Figure 2. S3032 Bit Error Rate (BER) Test Setup
S3032 BER TEST
BERT TX (622MHz)
DATA DATA CLOCK CLOCK
BERT RX
DATA CLOCK DATA
50 ohm
+1.2V +0.7V
S3032 DUT
RSDP 622MHz RSDN TSDP TSDN TSCLKP TSCLKN POWER SUPPLY DUT VCC = +2V
+0.2V
LSECL CONFIGURATION
DUT VEE = -1.3v +/- 5% GND = 0V DIP SWITCH SETTINGS: LLEB '1' SDPECL '1' DLEB '1' OOF '0' TESTEN '0' MODE1 '0' MODE0 '0' SLPTIME '0' FOR example 19.44MHz operation
REFCLKP
REFCLKN
TTLREF 10K +2v or not connected
HP8133 PULSE GENERATOR OR DIVIDER
EXT IN
(DIV BY 32) OUT 19.44MHz OUT
2
September 22, 1999
SONET/SDH/ATM OC-12 TRANSCEIVER EVALUATION BOARD
EV3032
Figure 3 depicts how two S3032 evaluation boards can be connected for BER measurements and jitter testing, and shows all of the DIP switch settings and the power supply requirements for use with test equipment that utilizes 50 to -2V termination. The DIP switch settings are for STS-12 testing.
Figure 3. S3032 BER Measurement and Jitter Test Setup
BERT RX(622.08MHz) 2 -1 PRBS
7
TEKTRONIX JITTER ANALYZER SJ300 (622.08MHz) THRU DATA REFCLK MEASURE JITTER GENERATION JITTERED OUTPUT DATA
BERT TX (622.08MHz) 27-1 PRBS DATA PATTERN
EXT IN
CLOCK
DATA OUTPUT
CLOCK
DATA
INPUT CLOCK
CLOCK CLOCK
-3.3V S3032 DUT(TX) TSCLKN TSDP TSCLKP RSDP RSDN TSDN REFCLKN FF00 HEX OR PRBS PATTERN DATA DATA
PIN 0 PIN 1 PIN 2 PIN 3 PIN 4 PIN 5 PIN 6 PIN 7
TTL BUS
S3032 DUT(RX)
POUT 0 POUT 1 POUT 2 POUT 3 POUT 4 POUT 5 POUT 6 POUT7
-3.3V
-3.3V LVECL BUFFER
RSDP RSDN
BERT TX(622.08MHz)
PICLK REFCLKP
POCLK REFCLKP REFCLKN
HP8133 OR DIVIDER (DIVIDE BY 32) OUT Provides Asynchronous Data POWER DIVIDERS OUT NOTE: At low frequency (10-30Hz) the reference clock must be Jittered Scope CASCADE MICROTECH ECL TERMINATOR VTT=-2.45V EXT CLK (155.52MHz)
VIH = -0.8 ECL INPUT LEVEL FOR ALL VIL = -1.8
DIP SWITCH SETTING
DUT VCC = 0V DUT VEE = -3.3V +/- 5% LLEB '1' SDPECL '1' DLEB '1' OOF '0' TESTEN '0' MODE1 '0' FOR 19.44MHz MODE0 '0' OPERATION SLPTIME '0'
MEASURE DATA EYE Trigger
September 22, 1999
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SONET/SDH/ATM OC-12 TRANSCEIVER EVALUATION BOARD
ELECTRICAL CONNECTIONS Power Connections
EV3032
Terminal posts are provided at the top edge of the board for VCC and VEE. The S3032 evaluation board can be configured with ECL, PECL and Level Shifted (LSECL) I/O so the board can be configured to operate with different types of standard test equipment. Figures 4 through 6 demonstrate the different types of input and output waveforms that the S3032 evaluation board can operate with the different voltage settings of VCC and VEE per Table 1. Note the TTL I/O's voltage level will change to non-standard levels when the S3032 evaluation board is powered by the different voltage. The external test equipment environment or other standard ECL and/or +3.3V referenced ECL systems can interface to the S3032 evaluation board. The board as shown in Figures 1 through 3 can be powered to allow easy connection to the 50 to ground inputs of high performance oscilloscopes and spectrum analyzers as well as the standard ECL I/O of serial Bit Error Rate Testers (BERT) and jitter analyzers. Table 1 illustrates the nominal input voltages for DUT VCC and VEE voltage levels shown in Figures 4 through 6. Figures 4 and 5 show that the voltages track with VEE, and Figure 6 shows that the voltages track with VCC.
Table 1. Power Connections for DUT and Test Equipment Interface
Power Supply DUT VCC DUT VEE DUT VCC DUT VEE DUT VCC DUT VEE Nominal Type of Signal Input Voltage +3.3 V 0V 0V -3.3 V +2V -1.3V LVPECL ECL Output Termination 50 to VCC-2V 50 to -2V 50 to GND
LVECL
LSECL
4
September 22, 1999
SONET/SDH/ATM OC-12 TRANSCEIVER EVALUATION BOARD
Figure 4. LVECL Signal Waveform
EV3032
LVECL VCC = 0V -0.8V -1.3V -1.8V VEE = -3.3V +/- 5% Termination = 50 to -2V
Figure 5. LSECL Signal Waveform
LSECL VCC = +2V +1.2V +0.7V +0.2V VEE = -1.3V +/- 5% Termination = 50 to GND
Figure 6. LVPECL Signal Waveform
LVPECL VCC = +3.3V +/- 5% 2.5V 2V 1.5V VEE = 0V Termination = 50 to (VCC -2V)
September 22, 1999
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