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Details, datasheet, quote on part number:S3457TT20
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| Part: | S3457TT20 |
| Category: | Communication => Network => SONET/SDH/ATM/DS3/PHYs/E3 (T3/E3) => Transceivers |
| Description: | OC-48 Sonet/sdh/atm 4-Bit Transceiver |
| Company: | AMCC (Applied Micro Circuits Corp) |
| Datasheet: | Download S3457TT20 datasheet File size : 199 kB |
| Request For quote: | Find where to buy S3457TT20
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Datasheet text preview:
Part Number S3457TT20 Revision PNC - June 29, 2001
S3457TT 20
OC-48 SONET/SDH/ATM 4-Bit Transceiver
FEATURES
· · · · · · · · · · · · · · · SiGe BiCMOS Technology Complies with Bellcore and ITU-T specifications 4-bit LVDS data path at 622.08 Mbps On-chip, high-frequency PLL for clock generation Supports OC-48 (2.488 Gbps) Reference frequency of 155.52 MHz Diagnostic loopback mode Supports line timing Lock detect Signal detect input Low jitter LVDS interface Internal FIFO to decouple transmit clocks Single 3.3 V supply Typical power 1.5 W Compact 128 Pin TQFP package · · · ·
DEVICE SPECIFICATION
Add Drop Multiplexers (ADM) Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
GENERAL DESCRIPTION
T h e S3457 SONET/SDH transceiver chip is a fully integrated serialization/deserialization SONET OC-48 (2.488 Gbps) interface device. The S3457 receives an OC-48 scrambled NRZ signal. The chip performs all necessary serial-to-parallel and parallel-to-serial functions in conformance with SONET/SDH transmission sta ndards. The device is suitable for SONET-based WDM applications. Figure 1 shows a typical network application. On-chip clock synthesis is performed by the high-frequency phase-lock loop on the S3457 transceiver chip, allowing the use of a slower external transmit clock refe r e n c e . The chip can be used with a 155.52 MHz reference clock in support of existing system clocking schemes. The low jitter LVDS interface guarantees compliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3457 is packaged in a compact 1 2 8 Pin TQFP, offering designers a small package outline.
APPLICATIONS
· · · · · · Wavelength Division Multiplex (WDM) equipment SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment ATM over SONET/SDH Section repeaters
Figure 1. System Block Diagram
4 4 4 4 AMCC GANGES AMCC S3457 S3056 4 4 4 4 AMCC S3457 S3056 AMCC S3457 S3056 AMCC S3457 S3056 OTX ORX ORX OTX 4 S3056 AMCC S3457 4
OTX ORX OTX ORX OTX ORX
ORX OTX ORX OTX ORX OTX
S3056
4 AMCC S3457 4 AMCC GANGES
S3056
4 AMCC S3457 4 4
S3056
AMCC S3457
4
AMCC Confidential and Proprietary
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S3457TT20 OC-48 SONET/SDH/ATM 4-Bit Transceiver SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard for connecting one fiber system to another at the optic a l level. SONET, together with the Synchronous Di g i t a l Hierarchy (SDH) administered by the ITU-T, forms a single international standard for fiber interconn e c t b e t w e e n telephone network s of di f f e r e n t c o u n t r i e s . SONET is capable of accommodating a variety of transmission rates and applications. The SONET standard is a layered protocol with four separate layers defined. These are: · · · · Photonic Section Line Path
Revision PNC - June 29, 2001
DEVICE SPECIFICATION
Frame and Byte Boundary Detection The SONET/SDH fundamental frame format for the STS-48 consists of 144 transport overhead bytes followed by the Synchronous Payload Envelope (SPE) b y te s . This pattern of 144 overhead and 4176 SPE bytes is repeated nine times in each frame. Frame and b y t e boundaries are detected using the A1 and A2 bytes found in the transport overhead. (See Figure 3.) For more details on SONET operations, refer to the Bellcore SONET standard document.
Figure 2. SONET Structure
Functions
Payload to SPE mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Path layer Line layer Section layer
Path layer Line layer Section layer
Figure 2 shows the layers and their functions. Each of t h e layers has overhead bandwidth dedicated to admini strati on and maintenance. The photonic layer easily handles the conversion from electrical to optical and back with no overhead. It is responsible for transmitti ng the electrical signals in optical form over the physical media. The section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. Key functions of this lay er are framing, scrambling, and error monitoring. The line layer is responsible for the reliable transmiss i o n of the path layer information stream carrying voice, data, and video signals. Its main functions are synchronization, multiplexing, and reliable transport. The path layer is responsible for the actual transport of services at the appropriate signaling rates. Data Rates and Signal Hierarchy Ta bl e 1 contains the data rates and signal designations of the SONET hierarchy. The lowest level is the basi c SONET signal referred to as the synchronous transpo rt signal level-1 (STS-1). An STS-N signal is m a d e up of N byte-interleaved STS-1 signals. The optical counterpart of each STS-N signal is an optical c a r r i e r level-N signal (OC-N). The S3457 chip supports the OC-48 rate (2.488 Gbps).
Photonic layer
Photonic layer
E n d Equipment
Fiber Cable E n d Equipment
Table 1. SONET Signal Hierarchy
Elec. STS-1 STS-3 STS-12 STS-24 STS-48 STM-1 STM-4 STM-8 STM-16 CCITT Optical OC-1 OC-3 OC-12 OC-24 OC-48 Data Rate (Mbps) 51.84 155.52 622.08 1244.16 2488.32
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AMCC Confidential and Proprietary
S3457TT20 OC-48 SONET/SDH/ATM 4-Bit Transceiver
Figure 3. STS-48/OC-48 Frame Format
A1 A1 A1 A1 A2 A2 48 A1 Bytes A2 A2 48 A2 Bytes
Revision PNC - June 29, 2001
DEVICE SPECIFICATION
9 Rows
Synchronous Payload Envelope 4176 Columns Transport Overhead 144 Columns 4176 x 9 = 37,584 bytes 144 x 9 = 1296 bytes 125 µsec
S3457 OVERVIEW
The S3457 transceiver implements SONET/SDH seriali za tion /des eria liz ati on and transmission functions. The block diagram in Figure 4 shows the basic operati on of the chip. This chip can be used to implement the front end of SONET equipment, which consists prima ri l y of the serial transmit interface and the serial receive interface. The chip handles all the functions of th e s e two elements, including parallel-to-serial and s e ri a l -t o -p a r a l l e l conversion, clock generation, and system timing. The system timing circuitry consists of management of the data stream and clock distribution throughout the front end.
The S3457 is divided into a transmitter section and a re c e i v e r section. The sequence of operations is as follows: Transmitter Operations: 1. 4-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver Operations: 1. Serial input 2. Serial-to-parallel conversion 3. 4-bit parallel output Internal clocking and control functions are transparent to the user.
Suggested Interface Devices
AMCC AMCC S3056 S19202 OC-48 Clock Recovery Device STS-192 POS/ATM SONET/SDH Mapper
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