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Part: A290021UL-70
Category:
Memory
-> Flash
Description: 70ns 20mA 1uA 256K X 8bit CMOS 5.0V-only
Company: AMIC Technology Corporation
Datasheet: Download A290021UL-70 datasheet File size : 168 kB
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Datasheet text preview:
A29002/A290021 Series
256K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
Features
n 5.0V ± 10% for read and write operations n Access times: - 55/70/90/120/150 (max.) n Current: - 20 mA typical active read current - 30 mA typical program/erase current - 1 µA typical CMOS standby n Flexible sector architecture - 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX3 sectors - Any combination of sectors can be erased - Supports full chip erase - Sector protection: A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector n Top or bottom boot block configurations available n Embedded Erase Algorithms - Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - Embedded Program algorithm automatically writes and verifies bytes at specified addresses n Typical 100,000 program/erase cycles per sector n 20-year data retention at 125°C - Reliable operation for the life of the system n Compatible with JEDEC-standards - Pinout and software compatible with single-powersupply Flash memory standard - Superior inadvertent write protection n Data Polling and toggle bits - Provides a software method of detecting completion of program or erase operations n Erase Suspend/Erase Resume - Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation n Hardware reset pin ( RESET ) - Hardware method to reset the device to reading array data (not available on A290021) n Package options - 32-pin P-DIP, PLCC, or TSOP (Forward type)
General Description
The A29002 is a 5.0 volt-only Flash memory organized as 262,144 bytes of 8 bits each. The A29002 offers the RESET function, but it is not available on A290021. The 256 Kbytes of data are further divided into seven sectors for flexible sector erase capability. The 8 bits of data appear on I/O0 I/O7 while the addresses are input on A0 to A17. The A29002 is offered in 32-pin PLCC, TSOP, and PDIP packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29002 can also be programmed in standard EPROM programmers. The A29002 has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29002 has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29002 also offers the ability to program in the Erase Suspend mode. The standard A29002 offers access times of 55, 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable ( CE ), write enable ( W E ) and output enable ( OE ) controls.
The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The A29002 is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin.
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A29002/A290021 Series
The host system can detect whether a program or erase operation is complete by reading the I/O7 ( Data Polling) and I/O6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29002 is fully erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved. Power consumption is greatly reduced when the device is placed in the standby mode. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data (This feature is not available on the A290021).
Pin Configurations
n DIP n PLCC
NC on A290021 1 2 3 4 VCC WE A17 4 3 2 1 32 RESET
NC on A290021
VCC
A12
A16
A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A15
31
A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13
30
A17
WE
RESET
32
A29002/A290021
5 6 7 8 9 10 11 12 13 14 15 16
29 28 27
A14 A13 A8 A9 A11 OE A10 CE I/O7
A29002L/ A290021L
26 25 24 23 22 21
14
15
16
17
18
19 I/O5
VSS
I/O1
I/O2
I/O3
I/O4
n TSOP (Forward type)
A11 A9 A8 A13 A14 A17 WE VCC RESET A16 NC on A290021 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3
A29002V/A290021V
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AMIC Technology, Corp.
I/O6
20
A29002/A290021 Series
Block Diagram
I/O0 - I/O7 VCC VSS
Erase Voltage Generator
Input/Output Buffers
WE RESET (N/A A290021)
State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE OE
Y-Decoder Address Latch STB VCC Detector Timer Y-Gating
X-decoder
A0-A17
Cell Matrix
Pin Descriptions
Pin No. A0 - A17 I/O0 - I/O7 Description Address Inputs Data Inputs/Outputs Chip Enable Write Enable Output Enable Hardware Reset (N/A A290021) Ground Power Supply
CE WE OE
RESET
VSS VCC
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A29002/A290021 Series
Absolute Maximum Ratings*
Ambient Operating Temperature . . . . . -55°C to + 125°C Storage Temperature . . . . . . . . . . . . . . -65°C to + 125°C Ground to VCC . . . . . . . . . . . . . . . . . . . . . . -2.0V to 7.0V Output Voltage (Note 1) . . . . . . . . . . . . . . . -2.0V to 7.0V A9, OE & RESET (Note 2) . . . . . . . . . . . -2.0V to 12.5V All other pins (Note 1) . . . . . . . . . . . . . . . . . -2.0V to 7.0V Output Short Circuit Current (Note 3) . . . . . . . . . . 200mA
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is VCC +0.5V. During voltage transitions, outputs may overshoot to VCC +2.0V for periods up to 20ns. 2. Minimum DC input voltage on A9 pins is -0.5V. During voltage transitions, A9, OE and RESET may overshoot VSS to -2.0V for periods of up to 20ns. Maximum DC input voltage on A9 and OE is +12.5V which may overshoot to 13.5V for periods up to 20ns. ( RESET is N/A on A290021) 3. No more than one output is shorted at a time. Duration of the short circuit should not be greater than one second.
Operating Ranges
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . 0°C to +70°C VCC Supply Voltages VCC for ± 10% devices . . . . . . . . . . . . . . +4.5V to +5.5V Operating ranges define those limits between which the functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to
execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1. A29002/A290021 Device Bus Operations Operation Read Write CMOS Standby TTL Standby
CE
L L VCC ± 0.5 V H
OE
L H X X
WE
H L X X
RESET
(N/A A290021) H H VCC ± 0.5 V VCC ± 0.5 V H L VID
A0 A17 AIN AIN X X
I/O0 - I/O7 DOUT DIN High-Z High-Z
Output Disable L H H X High-Z Reset X X X X High-Z Temporary Sector Unprotect (Note) X X X X X Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In Note: 1. See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information. 2. This function is not available on A290021.
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A29002/A290021 Series
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH all the time during read operation. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms, lCC1 in the DC Characteristics table represents the active current specification for reading array data. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE input. The device enters the CMOS standby mode when the CE & RESET pins ( CE only on A290021) are both held at VCC ± 0.5V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE is held at VIH, while RESET (Not available on A290021) is held at VCC±0.5V. The device requires the standard access time (tCE) before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics tables represents the standby current specification.
Output Disable Mode
When the OE input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE and CE to VIL, and OE to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on I/O7 - I/O0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information. ICC2 in the Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations.
RESET : Hardware Reset Pin (N/A on A290021)
The RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET parameters and diagram.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the status bits on I/O7 - I/O0. Standard read cycle timings and ICC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams.
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AMIC Technology, Corp.
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