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Part: A42L2604V-50U
Category:
Memory
-> DRAM
Description: 50ns; Refresh Recycle:2K; 4M X 4bit CMOS Dynamic RAM With Edo Page Mode
Company: AMIC Technology Corporation
Datasheet: Download A42L2604V-50U datasheet File size : 148 kB
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Datasheet text preview:
A42L2604 Series
Preliminary
Document Title 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History
Rev. No.
0.0 0.1 0.2
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
History
Initial issue Modify symbol HE dimensions in TSOP 24L package information Add -45 grade and modify the AC, DC data Add -U type spec.
Issue Date
June 13, 2001 July 10, 2001 November 30, 2001
Remark
Preliminary
Preliminary
(November, 2001, Version 0.2)
AMIC Technology, Inc.
A42L2604 Series
Preliminary
Features
n Organization: 4,194,304 words X 4 bits n Part Identification - A42L2604 (2K Ref.) - A42L2604-L (2K Ref. with self-refresh) n Single 3.3V power supply/built-in VBB generator n Low power consumption - Operating: 80mA (-45 max) - Standby: 1mA (TTL), 1mA (CMOS), 350µA (Self-refresh current) n High speed - 45/50 ns RAS access time - 20/22 ns column address access time - 12/13 ns CAS access time - 18/20 ns EDO Page Mode Cycle Time n Industrial operating temperature range: -40°C to +85°C for -U n Fast Page Mode with Extended Data Out n 2K Refresh Cycle in 32ms n Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 300mil, 24/26-pin SOJ - 300mil, 24/26-pin TSOP type II package
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
General Description
The A42L2604 is a new generation randomly accessed memory for graphics, organized in a 4,194,304-word by 4-bit configuration. This product can execute Write and Read operation via CAS pin. The A42L2604 offers an accelerated Fast Page Mode cycle with a feature called Extended Data Out (EDO). This allow random access of up to 2048(2K Ref.) words within a row at a 56/50 MHz EDO cycle, making the A42L2604 ideally suited for graphics, digital signal processing and high performance computing systems.
Pin Configuration n SOJ n TSOP Pin Descriptions
26 25 24 23 VSS I/O 3 I/O 2 CAS OE A9 A8 A7 A6 A5 A4 VSS
VCC I/O 0 I/O 1 WE RAS NC A10 A0 A1 A2 A3 VCC
1 2 3 4
26 25 24 23
VSS I/O 3 I/O 2 CAS OE A9 A8 A7 A6 A5 A4 VSS
VCC I/O 0 I/O 1 WE RAS NC A10 A0 A1 A2 A3 VCC
1 2 3 4
Symbol A0 A10 I/O0 - I/O3 RAS
Description Address Inputs (2K product) Data Input/Output Row Address Strobe Column Address Strobe Write Enable Output Enable 3.3V Power Supply Ground No Connection
A42L2604S
A42L2604V
5 6 8 9 10 11 12 13
22 21 19 18 17 16 15 14
5 6 8 9 10 11 12 13
22 21 19 18 17 16 15 14
CAS
WE
OE VCC VSS NC
PRELIMINARY
(November, 2001, Version 0.2)
1
AMIC Technology, Inc.
A42L2604 Series
Selection Guide
Symbol tRAC tAA tCAC tOEA tRC tPC Description Maximum RAS Access Time Maximum Column Address Access Time Maximum CAS Access Time Maximum Output Enable ( OE ) Access Time Minimum Read or Write Cycle Time Minimum EDO Cycle Time -45 45 20 12 12 76 18 -50 50 22 13 13 84 20 Unit ns ns ns ns ns ns
Functional Description
The A42L2604 reads and writes data by multiplexing an 22-bit address into a 11-bit(2K) row and column address. RAS and CAS are used to strobe the row address and the column address, respectively. A Read cycle is performed by holding the WE signal high during RAS / CAS operation. A Write cycle is executed by holding the WE signal low during RAS / CAS operation; the input data is latched by the falling edge of WE or CAS , whichever occurs later. The data inputs and outputs are routed through 4 common I/O pins, with RAS , CAS , WE and OE controlling the in direction. EDO Page Mode operation all 2048(2K) columns within a selected row to be randomly accessed at a high data rate. A EDO Page Mode cycle is initiated with a row address latched by RAS followed by a column address latched by CAS . While holding RAS low, CAS can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A42L2604 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the CAS precharge time (tcp). Since data can be output after CAS goes high, the user is not required to wait for valid data to appear before starting the next access cycle. Data-out will remain valid as long as RAS and OE are low, and WE is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A memory cycle is terminated by returning both RAS and CAS high. Memory cell data will retain its correct state by maintaining power and accessing all 2048(2K) combinations of the 11-bit(2K) row addresses, regardless of sequence, at least once every 32ms through any RAS cycle (Read, Write) or RAS Refresh cycle ( RAS -only, CBR, or Hidden). The CBR Refresh cycle automatically controls the row addresses by invoking the refresh counter and controller.
Power-On
The initial application of the VCC supply requires a 200 µs wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS . It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
PRELIMINARY
(November, 2001, Version 0.2)
2
AMIC Technology, Inc.
A42L2604 Series
Block Diagram
RAS CAS WE
Vcc Control Clocks VBB Generator Vss
Refresh Timer
Row Decoder Data in Buffer Sense Amps & I/O
Refresh control Memory Array 4,194,304 X 4 Cells
I/O0 to I/O3
Refresh Counter
Data out Buffer
OE
A0~A10
Row Address Buffer
A0~A10
Col. Address Buffer
Column Decoder
Recommended Operating Conditions
Symbol VCC VSS VIH VIL Description Power Supply Input High Voltage Input High Voltage Input Low Voltage
(Ta = 0°C to +70°C or -40°C to +85°C) Min. 3.0 0 2.0 -1.0 Typ. 3.3 0 Max. 3.6 0 VCC + 0.3 0.8 Unit V V V V
PRELIMINARY
(November, 2001, Version 0.2)
3
AMIC Technology, Inc.
A42L2604 Series
Truth Table
Function Standby Read: Word Read Write: Word (Early) Write (Early) Read-Write EDO-Page-Mode Read: Hi-Z -First cycle -Subsequent Cycles EDO-Page-Mode Write (Early) -First cycle -Subsequent Cycles EDO-Page-Mode Read-Write -First cycle -Subsequent Cycles Hidden Refresh Read Hidden Refresh Write RAS -Only Refresh CBR Refresh Self Refresh (L-ver only) RAS H L L L L L L L L L L L LHL LHL L HL HL
CAS
H L L L L L HL HL HL HL HL HL L L H L L
WE X H H L L HL H H L L HL HL H L X X H
OE X L L X X LH HL HL X X LH LH L X X X X
Address X Row/Col. Row/Col. Row/Col. Row/Col. Row/Col. Row/Col. Col. Row/Col. Col. Row/Col. Col. Row/Col. Row/Col. Row X X
I/Os High-Z Data Out Data Out Data In Data In Data Out Data In Data Out Data Out Data In Data In Data Out Data In Data Out Data In Data Out Data In High-Z High-Z High-Z High-Z
PRELIMINARY
(November, 2001, Version 0.2)
4
AMIC Technology, Inc.
Others parts begin by a4
A4-1 A4-2 A4-3
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