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Part: A42L8316S
Category:
Memory
-> DRAM
Description: 30ns; Self Refresh 256K X 16 CMOS Dynamic RAM With Edo Page Moge
Company: AMIC Technology Corporation
Datasheet: Download A42L8316S datasheet File size : 148 kB
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A42L8316 Series
Preliminary
Document Title 256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History
Rev. No.
0.0 0.1 0.2
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
History
Initial issue Modify AC data Delete the -30 grade
Issue Date
January 26, 1999 August 20, 2002 November 1, 2002
Remark
Preliminary
PRELIMINARY
(November, 2002, Version 0.2)
AMIC Technology, Corp.
A42L8316 Series
Preliminary
Features
n Organization: 262,144 words X 16 bits n Part Identification - A42L8316 (512 Ref.) n Single 3.3V power supply/built-in VBB generator n Low power consumption - Operating: 105mA (-35 max) - Standby: 2.5mA (TTL), 1.5mA (CMOS) 1.0mA (Self-refresh current) n High speed - 35/40 ns RAS access time - 17/18 ns column address access time - 10/11 ns CAS access time - 16/18 ns EDO Page Mode Cycle Time n Industrial operating temperature range: -40°C to 85°C for -U n Fast Page Mode with Extended Data Out n Separate CAS ( UCAS , LCAS ) for byte selection n 512 Refresh Cycle in 8ms n Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 400mil, 40-pin SOJ - 400mil, 40/44 TSOP type II package
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
General Description
The A42L8316 is a new generation randomly accessed memory for graphics, organized in a 262,144-word by 16bit configuration. This product can execute Byte Write and Byte Read operation via two CAS pins. The A42L8316 offers an accelerated Fast Page Mode
This allow random access of up to 512 words within a row at a 62/55 MHz EDO cycle, making the A42L8316 ideally suited for graphics, digital signal processing and high performance computing systems.
Pin Descriptions
Symbol A0 A8 I/O0 - I/O15 RAS Description Address Inputs Data Input/Output Row Address Strobe Column Address Strobe for Lower Byte (I/O0 I/O7) Column Address Strobe for Upper Byte (I/O8 I/O15) WE OE VCC VSS NC Write Enable Output Enable 3.3V Power Supply Ground No Connection
Pin Configuration n SOJ
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
n TSOP
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
LCAS
UCAS
cycle with a feature called Extended Data Out (EDO).
PRELIMINARY
A42L8316S
(November, 2002, Version 0.2)
A42L8316V
1
AMIC Technology, Corp.
A42L8316 Series
Selection Guide
Symbol tRAC tAA tCAC tOEA tRC tPC Description Maximum RAS Access Time Maximum Column Address Access Time Maximum CAS Access Time Maximum Output Enable ( OE ) Access Time Minimum Read or Write Cycle Time Minimum EDO Cycle Time -35 35 17 10 10 62 16 -40 40 18 11 11 70 18 Unit ns ns ns ns ns ns
Functional Description
The A42L8316 reads and writes data by multiplexing an 18-bit address into a 9-bit row and 9-bit column address. RAS and CAS are used to strobe the row address and the column address, respectively. The A42L8316 has two CAS inputs: LCAS controls I/O0I/O7, and UCAS controls I/O8 - I/O15, UCAS and LCAS function in an identical manner to CAS in that either will generate an internal CAS signal. The CAS function and timing are determined by the first CAS ( UCAS or LCAS ) to transition low and by the last to transition high. Byte Read and Byte Write are controlled by using LCAS and UCAS separately. A Read cycle is performed by holding the WE signal high during RAS / CAS operation. A Write cycle is executed by holding the WE signal low during RAS / CAS operation; the input data is latched by the falling edge of WE or CAS , whichever occurs later. The data inputs and outputs are routed through 16 common I/O pins, with RAS , CAS , WE and OE controlling the in direction. EDO Page Mode operation all 512 columns within a selected row to be randomly accessed at a high data rate. A EDO Page Mode cycle is initiated with a row address latched by RAS followed by a column address latched by CAS . While holding RAS low, CAS can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A42L8316 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the CAS precharge time (tcp). Since data can be output after CAS goes high, the user is not required to wait for valid data to appear before starting the next access cycle. Data-out will remain valid as long as RAS and OE are low, and WE is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A memory cycle is terminated by returning both RAS and CAS high. Memory cell data will retain its correct state by maintaining power and accessing all 512 combinations of the 9-bit row addresses, regardless of sequence, at least once every 8ms through any RAS cycle (Read, Write) or RAS Refresh cycle ( RAS -only, CBR, or Hidden). The CBR Refresh cycle automatically controls the row addresses by invoking the refresh counter and controller.
Power-On
The initial application of the VCC supply requires a 200 µs wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS . It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
PRELIMINARY
(November, 2002, Version 0.2)
2
AMIC Technology, Corp.
A42L8316 Series
Block Diagram
OE WE UCAS LCAS WE Clock Generator CAS Clock Generator OE Clock Generator
I/O0
Column Address Buffers AY0 - AY8 Column Decoders Data I/O Buffers
to I/O15
Sense Amplifiers
A0 - A8
Refresh Counter & Controller . . . 512 . . . ROW DECODER
..
512 x 16 .
.
Row Address Buffers
AX0 - AX8
Memory Array 512 x 512 x 16
RAS
RAS Clock Generator
VCC VSS
Recommended Operating Conditions
Symbol VCC VSS VIH VIL Description Power Supply Input High Voltage Input High Voltage Input Low Voltage
(Ta = 0°C to +70°C or -40°C to +85°C) Min. 3.0 0.0 2.0 -0.5 Typ. 3.3 0.0 Max. 3.6 0.0 VCC + 0.3 0.8 Unit V V V V Notes 1 1 1 1
PRELIMINARY
(November, 2002, Version 0.2)
3
AMIC Technology, Corp.
A42L8316 Series
Truth Table
Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word Write: Lower Byte Write: Upper Byte Read-Write EDO-Page-Mode Read: Hi-Z -First cycle -Subsequent Cycles EDO-Page-Mode Write -First cycle -Subsequent Cycles EDO-Page-Mode Read-Write -First cycle -Subsequent Cycles Hidden Refresh Read Hidden Refresh Write RAS -Only Refresh CBR Refresh Self Refresh Note: RAS H L L L L L L L L L L L L L LHL LHL L HL HL
UCAS
H L H L L H L L HL HL HL HL HL HL L L H L L
LCAS
H L L H L L H L HL HL HL HL HL HL L L H L L
WE X H H H L L L HL H H L L HL HL H L X X H
OE X L L L H H H LH HL HL H H LH LH L X X X X
Address X Row/Col. Row/Col. Row/Col. Row/Col. Row/Col. Row/Col. Row/Col. Row/Col. Col. Row/Col. Col. Row/Col. Col. Row/Col. Row/Col. Row X X
I/Os High-Z Data Out I/O0-7 = Data Out I/O8-15 = High-Z I/O0-7 = High-Z I/O8-15 = Data Out Data In I/O0-7 = Data In I/O8-15 = X I/O0-7 = X I/O8-15 = Data In Data Out Data In Data Out Data Out Data In Data In Data Out Data In Data Out Data In Data Out Data In High-Z High-Z High-Z High-Z
Notes
1,2 2 2 1 1 1, 2 1, 2 2 1 3
1. Byte Write may be executed with either UCAS or LCAS active. 2. Byte Read may be executed with either UCAS or LCAS active. 3. Only one CAS signal ( UCAS or LCAS ) must be active.
PRELIMINARY
(November, 2002, Version 0.2)
4
AMIC Technology, Corp.
Others parts begin by a4
A4-1 A4-2 A4-3
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