Log in
Details, datasheet, quote on part number: A42U0616
CategoryMemory => DRAM
DescriptionDRAM Sdram Sgram 16Mb X16
CompanyAMIC Technology Corporation
DatasheetDownload A42U0616 datasheet
QuoteFind where to buy A42U0616


Features, Applications
Document Title X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History

n Organization: 1,048,576 words X 16 bits n Part Identification A42U0616 (1K Ref.) n Single 2.5V power supply/built-in VBB generator n Low power consumption - Operating: 120mA (-50 max) - Standby: 1mA (TTL), 0.2mA (CMOS), 250A (Self-refresh current) n High speed 50/60/80 ns RAS access time 25/30/40 ns column address access time 13/15/20 ns CAS access time 20/25/35 ns EDO Page Mode Cycle Time n Separate CAS ( UCAS , LCAS ) for byte selection n Fast Page Mode with Extended Data Out n Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages 400mil, 42-pin SOJ 400mil, 50/44 TSOP type II package

The is a new generation randomly accessed memory for graphics, organized a 1,048,576 -word by 16-bit configuration. This product can execute Write and Read operation via CAS pin. The A42U0616 offers an accelerated Fast Page Mode cycle with a feature called Extended Data Out (EDO). This allow random access to 1024(1K Ref.) words within a row a 50/40/28 MHz EDO cycle, making the A42U0616 ideally suited for graphics, digital signal processing and high performance computing systems.

Description Address Inputs (1K product) Data Input/Output Row Address Strobe Column Address Strobe for Lower Byte I/O7)

Column Address Strobe for Upper Byte I/O15) Write Enable Output Enable 2.5V Power Supply Ground No Connection

Symbol tRAC tAA tCAC tOEA tRC tPC Description Maximum RAS Access Time Maximum Column Address Access Time Maximum CAS Access Time Maximum Output Enable OE ) Access Time Minimum Read or Write Cycle Time Minimum EDO Cycle Time Unit ns

The A42U0616 reads and writes data by multiplexing an 20-bit address into a 10-bit row and 10-bit column address. RAS and CAS are used to strobe the row address and the column address, respectively. The A42U0616 has two CAS inputs: LCAS controls I/O0I/O7, and UCAS controls - I/O15, UCAS and LCAS function in an identical manner to CAS in that either will generate an internal CAS signal. The CAS function and timing are determined by the first CAS ( UCAS or LCAS ) to transition low and by the last to transition high. Byte Read and Byte Write are controlled by using LCAS and UCAS separately. A Read cycle is performed by holding the WE signal high during RAS/ CAS operation. A Write cycle is executed by holding the WE signal low during RAS/ CAS operation; the input data is latched by the falling edge WE or CAS , whichever occurs later. The data inputs and outputs are routed through 16 common I/O pins, with RAS, CAS , WE and OE controlling the in direction. EDO Page Mode operation all 1024(1K) columns within a selected row to be randomly accessed at a high data rate. A EDO Page Mode cycle is initiated with a row address latched by RAS followed by a column address latched by CAS. While holding RAS low, CAS can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A42U0616 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the CAS precharge time (tcp). Since data can be output after CAS goes high, the user is not required to wait for valid data to appear before starting the next access cycle. Data-out will remain valid as long as RAS and OE are low, and WE is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A memory cycle is terminated by returning both RAS and CAS high. Memory cell data will retain its correct state by maintaining power and accessing all 1024(1K) combinations of the 10-bit row addresses, regardless of sequence, at least once every 16ms through any RAS cycle (Read, Write) or RAS Refresh cycle (RAS -only, CBR, or Hidden). The CBR Refresh cycle automatically controls the row addresses by invoking the refresh counter and controller.

The initial application of the VCC supply requires 200 s wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS. It is recommended that RAS and CAS track with VCC or be held at a valid V IH during Power-On to avoid current surges.

Related products with the same datasheet
Some Part number from the same manufacture AMIC Technology Corporation
A42U0616S DRAM Sdram Sgram 16Mb X16
A42U2604 DRAM Sdram Sgram 16Mb x4
A43L0616 DRAM Sdram Sgram 16Mb X16
A43L0616AV-55 512k X 16 Bit X 2 Banks Synchronous DRAM
A43L0616AV-6 DRAM Sdram Sgram 16Mb X16
A43L2616 DRAM Sdram Sgram 64Mb X16
A43L8316 DRAM Sdram Sgram 4Mb X16
A45L9332A DRAM Sdram Sgram 16Mb X32
A46L1632E DRAM Sdram Sgram 64Mb X32
A615308 SRAM High Speed Asynchronous 0.25Mb x8
A616316 64k X 16 Bit High Speed CMOS SRAM
A617308 SRAM High Speed Asynchronous 1Mb x8
A6173081 128k X 8 Bit High Speed CMOS SRAM
A6173081S-12 SRAM High Speed Asynchronous 1Mb x8
A61L6316 SRAM High Speed Asynchronous 1Mb X16
0-C     D-L     M-R     S-Z     0-C     D-L     M-R     S-Z