Details, datasheet, quote on part number: A42U0616
CategoryMemory => DRAM
DescriptionDRAM Sdram Sgram 16Mb X16
CompanyAMIC Technology Corporation
DatasheetDownload A42U0616 datasheet
Cross ref.Similar parts: MSM51X18160
Find where to buy


Features, Applications
Document Title X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History

n Organization: 1,048,576 words X 16 bits n Part Identification A42U0616 (1K Ref.) n Single 2.5V power supply/built-in VBB generator n Low power consumption - Operating: 120mA (-50 max) - Standby: 1mA (TTL), 0.2mA (CMOS), 250A (Self-refresh current) n High speed 50/60/80 ns RAS access time 25/30/40 ns column address access time 13/15/20 ns CAS access time 20/25/35 ns EDO Page Mode Cycle Time n Separate CAS ( UCAS , LCAS ) for byte selection n Fast Page Mode with Extended Data Out n Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages 400mil, 42-pin SOJ 400mil, 50/44 TSOP type II package

The is a new generation randomly accessed memory for graphics, organized a 1,048,576 -word by 16-bit configuration. This product can execute Write and Read operation via CAS pin. The A42U0616 offers an accelerated Fast Page Mode cycle with a feature called Extended Data Out (EDO). This allow random access to 1024(1K Ref.) words within a row a 50/40/28 MHz EDO cycle, making the A42U0616 ideally suited for graphics, digital signal processing and high performance computing systems.

Description Address Inputs (1K product) Data Input/Output Row Address Strobe Column Address Strobe for Lower Byte I/O7)

Column Address Strobe for Upper Byte I/O15) Write Enable Output Enable 2.5V Power Supply Ground No Connection

Symbol tRAC tAA tCAC tOEA tRC tPC Description Maximum RAS Access Time Maximum Column Address Access Time Maximum CAS Access Time Maximum Output Enable OE ) Access Time Minimum Read or Write Cycle Time Minimum EDO Cycle Time Unit ns

The A42U0616 reads and writes data by multiplexing an 20-bit address into a 10-bit row and 10-bit column address. RAS and CAS are used to strobe the row address and the column address, respectively. The A42U0616 has two CAS inputs: LCAS controls I/O0I/O7, and UCAS controls - I/O15, UCAS and LCAS function in an identical manner to CAS in that either will generate an internal CAS signal. The CAS function and timing are determined by the first CAS ( UCAS or LCAS ) to transition low and by the last to transition high. Byte Read and Byte Write are controlled by using LCAS and UCAS separately. A Read cycle is performed by holding the WE signal high during RAS/ CAS operation. A Write cycle is executed by holding the WE signal low during RAS/ CAS operation; the input data is latched by the falling edge WE or CAS , whichever occurs later. The data inputs and outputs are routed through 16 common I/O pins, with RAS, CAS , WE and OE controlling the in direction. EDO Page Mode operation all 1024(1K) columns within a selected row to be randomly accessed at a high data rate. A EDO Page Mode cycle is initiated with a row address latched by RAS followed by a column address latched by CAS. While holding RAS low, CAS can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A42U0616 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the CAS precharge time (tcp). Since data can be output after CAS goes high, the user is not required to wait for valid data to appear before starting the next access cycle. Data-out will remain valid as long as RAS and OE are low, and WE is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A memory cycle is terminated by returning both RAS and CAS high. Memory cell data will retain its correct state by maintaining power and accessing all 1024(1K) combinations of the 10-bit row addresses, regardless of sequence, at least once every 16ms through any RAS cycle (Read, Write) or RAS Refresh cycle (RAS -only, CBR, or Hidden). The CBR Refresh cycle automatically controls the row addresses by invoking the refresh counter and controller.

The initial application of the VCC supply requires 200 s wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS. It is recommended that RAS and CAS track with VCC or be held at a valid V IH during Power-On to avoid current surges.


Related products with the same datasheet
Some Part number from the same manufacture AMIC Technology Corporation
A42U0616S DRAM Sdram Sgram 16Mb X16
A42U2604 DRAM Sdram Sgram 16Mb x4
A43L0616 DRAM Sdram Sgram 16Mb X16
A43L0616AV-55 512k X 16 Bit X 2 Banks Synchronous DRAM
A43L0616AV-6 DRAM Sdram Sgram 16Mb X16
A43L2616 DRAM Sdram Sgram 64Mb X16
A43L8316 DRAM Sdram Sgram 4Mb X16
A45L9332A DRAM Sdram Sgram 16Mb X32
A46L1632E DRAM Sdram Sgram 64Mb X32
A615308 SRAM High Speed Asynchronous 0.25Mb x8
A616316 64k X 16 Bit High Speed CMOS SRAM
A617308 SRAM High Speed Asynchronous 1Mb x8
A6173081 128k X 8 Bit High Speed CMOS SRAM
A6173081S-12 SRAM High Speed Asynchronous 1Mb x8
A61L6316 SRAM High Speed Asynchronous 1Mb X16
Same catergory

AT24C1024 : . 2.7 (VCC to 5.5V) Internally Organized 8 2-wire Serial Interface Schmitt Triggers, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol 400 kHz (2.7V) and 1 MHz (5V) Clock Rate Write Protect Pin for Hardware and Software Data Protection 256-byte Page Write Mode (Partial Page Writes Allowed) Random and Sequential Read Modes Self-timed.

DPS512S8U : 512kx8 CMOS SRAM. The X 8 high-density, low-power static RAM module comprised of four X 8 monolithic SRAM's, an advanced high-speed CMOS decoder and decoupling capacitors surface mounted on an epoxy laminate substrate. The DPS512S8U operates from a single +5V supply and all input and output pins are completely TTL-compatible. The low standby power of the DPS512S8U makes.

HEF4505BF : 64-bit, 1-bit Per Word Random Access Read/write Memory. For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family s HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC Product File under Integrated Circuits, IC04 January 1995 The 64-bit, 1-bit per word, fully decoded and completely static, random access memory. The memory is strobed for reading or writing.

HYM71V16655BLT6-8 : ->Unbuffered DIMM. based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh The Hynix HYM71V16655BT6 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 8Mx16bits CMOS Synchronous DRAMs 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package a 168pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors.

IS61NF25632 : 256Kx32 Flow-through 'NO WAIT' State Bus SRAM. 100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining for TQFP.

K9D1G08V0M : Smart Media->128M Byte. = K9D1G08V0M 128MB SmartMedia(TM) Card ;; Organization = 128Mx8 ;; Operating Voltage(V) = 2.7~3.6 ;; Temperature = 0~55 ;; Speed(ns) = 50 ;; Package = 22PAD ;; Production Status = Mass Production ;; Comments = -.

KT3272SSN0R : ->DIMM. This memory module is a high performance 256 Megabyte Registered synchronous dynamic RAM module organized in one Bank a 168 pin Low Dual In-Line Memory Module (DIMM) package. The module utilizes eighteen (18) 8Mx4X4 SDRAM (64ms Refresh) devices in a TSOP II 400 mil package. A 256 Byte Serial EEPROM contains the module configuration information. The EEPROM.

M36W432-ZAT : 32 Mbit 2mb X16, Boot Block Flash Memory And 4 Mbit 256k X16 SRAM, Multiple Memory Product.

M5M5V108CFP-10H : 1048576-bit (131072-word BY 8-bit) CMOS Static RAM. The M5M5V108CFP,VP,RV,KV,KR are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using high-performance quadruple-polysilicon and double metal CMOS technology. The use of thin film transistor (TFT) load cells and CMOS periphery result in a high density and low power static RAM. They are low standby current and low operation.

MSM27C401CZ : 512k X 8 OTP ROM. The a 4Mbit electrically Programmable Read-Only Memory organized as 524,288 word x 8bit. The MSM27C401CZ operates on a single +3V-5V power supply and is TTL compatible. Since the MSM27C401CZ operates asynchronously , external clocks are not required , making this device easy-to-use. The MSM27C401CZ is suitable as large-capacity fixed memory for microcomputers.

MTCF004 : CompactFlash. Implements a highly integrated memory controller Fully compatible with CompactFlashTM ATA (IDE) compatible 16-bit PC Card ATA standard with optional adapter Also PCMCIA 2.1 compatible with optional adapter Smallest ATA-compatible form factor x 3.3mm Uses standard ATA software drivers; no additional software drivers required High reliability No moving.

STK15C68 : SRAM. Density = 64K ;; Format = 8K X 8 ;; # of Pins = 28 ;; Access Time (ns MAX) =  25,35,45 ;; Initiated Store = Autostore ;; Production = Now ;; Volt = 5 ;; Temps Commercial Industrial Military = C/i.

TM8SP64KPN : 8,388,608 BY 64-bit Sdram Module (dimm). Organization: x 64 Bits x 64 Bits Single 3.3-V Power Supply (10% Tolerance) Designed for 66-MHz 4-Clock Systems JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket TM4SP64KPN Uses Four 64M-Bit Synchronous Dynamic RAMs (SDRAMs) 16-Bit) in Plastic Thin Small-Outline Packages (TSOPs) TM8SP64KPN Uses Eight 64M-Bit SDRAMs.

V54C333322V : 200/183/166 MHZ 3.3 Volt Ultra High Performance 1M X 32 Sdram 2 Banks X 512Kbit X 32.

X25043 : Programmable Watchdog Supervisory E2PROM. Programmable Watchdog Timer Low VCC Detection Reset Signal Valid to VCC 1V 1MHz Clock Rate X 8 Bits Serial E2PROM --4 Byte Page Mode Low Power CMOS --50A Standby Current --3mA Active Current To 5.5V Power Supply Block LockTM --Protect 1/2 or all of E2PROM Array Built-in Inadvertent Write Protection --Power-Up/Power-Down protection circuitry --Write.

238A792-131 : 128K X 32 MULTI DEVICE SRAM MODULE, 35 ns, CDFP64. s: Memory Category: SRAM Chip ; Density: 4194 kbits ; Number of Words: 128 k ; Bits per Word: 32 bits ; Package Type: 1 X 0.900 INCH, CERAMIC, DFP-64 ; Pins: 64 ; Logic Family: CMOS ; Supply Voltage: 3.3V ; Access Time: 35 ns ; Operating Temperature: -55 to 125 C (-67 to 257 F).

0-C     D-L     M-R     S-Z