JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2,3) - Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) n All inputs are sampled at the positive going edge of the system clock n Clock Frequency: CL=3 n Burst Read Single-bit Write operation n DQM for masking n Auto & self refresh n 64ms refresh period (4K cycle) n 54 Pin TSOP (II)
The is 67,108,864 bits synchronous high data rate Dynamic RAM organized X 1,048,576 words by 16 bits, fabricated with AMIC's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Symbol CLK CS Name System Clock Chip Select Description Active on the positive going edge to sample all inputs. Disables or Enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle. CKE Clock Enable CKE should be enabled at least one clock + tss prior to new command. Disable input buffers for power down in standby. Row / Column addresses are multiplexed on the same pins. A0~A11 Address Row address : RA0~RA11, Column address: CA0~CA7 Selects bank to be activated during row address latch time. BS0, BS1 Bank Select Address Selects band for read/write during column address latch time. Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and Row precharge. Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power Supply: +3.3Vą0.3V/Ground Provide isolated Power/Ground to DQs for improved noise immunity.