JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Dual banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2,3) - Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM 0-3 for byte masking Auto & self refresh 32ms refresh period (2K cycle) n 100 Pin QFP, LQFP X 20 mm)

n SMRS cycle - Load mask register - Load color register n Write Per Bit (Old Mask) n Block Write (8 Columns)

The is 16,777,216 bits synchronous high data rate Dynamic RAM organized X 262,144 words by 32 bits, fabricated with AMIC's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. Write per bit and 8 columns block write improves performance in graphics system.

DQ 3 VDDQ DQ 5 VSSQ 6 DQ7 VDDQ DQ 17 VSSQ DQ 19 VDDQ VDD VSS DQ 21 VSSQ DQ 23 VDDQ DQM2 WE CAS RAS BA(A10) A8

DQ28 VDDQ DQ 26 VSSQ DQ 24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ DQM3 DQM1 CLK CKE DSF NC A9