Details, datasheet, quote on part number: A62S7308BM-55S
PartA62S7308BM-55S
Category
DescriptionSRAM Low Power & Low Voltage 1Mb x8
CompanyAMIC Technology Corporation
DatasheetDownload A62S7308BM-55S datasheet
Quote
Find where to buy
 
  

 

Features, Applications
Document Title X 8 BIT LOW VOLTAGE CMOS SRAM Revision History

Initial issue Change max. power supply voltage from to 3.6V Change min. VIH from to 2.4V Add feature "Interfaces directly with 3.3V typ. logic chip" Remove A62S7308B-10S/SI part

Add A62S7308B-55S/SI part Change Input Pulse Levels from in AC Test Conditions table
Features

n Power supply range: 3.6V n Access times: 55ns (max.): for VCC 3.6V 70ns (max.): for VCC 3.6V n Current: A62S7308B-S series: Operating: 30mA (max.) Standby: 5A (max.) A62S7308B-SI series: Operating: 30mA (max.) Standby: 10A (max.) n Extended operating temperature range: to 85C for -SI series Full static operation, no clock or refreshing required All inputs and outputs are directly TTL compatible Common I/O using three-state output Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32-pin SOP, TSOP, sTSOP (8X 13.4mm) forward type and 36-ball Mini BGA (6X8) packages n Interfaces directly with 3.3V typ. logic chip

The is a low operating current 1048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a low power supply voltage from to 3.6V. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for power down and a device enable and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V.


Description Address Inputs Write Enable Chip Enable 2 Power Supply No Connection Data Inputs/Outputs Ground Chip Enable 1 Output Enable

Data Inputs/Outputs Ground Chip Enable 1 Output Enable Write Enable Chip Enable 2 Power Supply

 

Related products with the same datasheet
A62S7308B-55S
A62S7308B-55SI
A62S7308B-70S
A62S7308B-70SI
A62S7308B-S
A62S7308B-SI
A62S7308BG-55S
A62S7308BG-55SI
A62S7308BG-70S
A62S7308BG-70SI
A62S7308BM
Some Part number from the same manufacture AMIC Technology Corporation
A62S7308BM-55SI SRAM Low Power & Low Voltage 1Mb x8
A62S7316 SRAM Low Power & Low Voltage 2Mb X16
A62S7332E-4.2 4.2ns 128K X 32bit Synchronous High Speed SRAM
A62S7332E-4.5 4.5ns 128K X 32bit Synchronous High Speed SRAM
A62S7332E-5 5ns 128K X 32bit Synchronous High Speed SRAM
A62S8308 SRAM Low Power & Low Voltage 2Mb x8
A62S8316 SRAM Low Power & Low Voltage 4Mb X16
A62S9308 SRAM Low Power & Low Voltage 4Mb x8
A63G7332 SRAM High Speed Synchronous 4Mb X32
A63G7332E-42 128k X 32 Bit Synchronous High Speed SRAM With Burst Counter And Pipelined Data Output
A63G7332E-5 SRAM High Speed Synchronous 4Mb X32
A63L7332
A63L73321
A63L7332E-4.2
A63L7332E-42 128k X 32 Bit Synchronous High Speed SRAM With Burst Counter And Pipelined Data Output
A63L7332E-5 SRAM High Speed Synchronous 4Mb X32
A64E06161 16 Mb, 1M X 16,

A29002TL-150 : Flash 2Mb x8

A42L0616S-50L : DRAM Sdram Sgram 16Mb X16

A42L8316V-30 : 30ns; Self Refresh 256K X 16 CMOS Dynamic RAM With Edo Page Moge

A67P0636E-2.8 : 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67P1618, A67P0636 SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit

A67P9318E-3.5F : 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67P9318, A67P8336 SRAMs integrate a 512K X 18, 256K X 36 SRAM core with advanced synchronous peripheral circuitry and

A67L8318E-3.2F : 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L8318, A67L7336 SRAMs integrate a 256K X 18, 128K X 36 SRAM core with advanced synchronous peripheral circuitry and

A67P7336E-2.8 : 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67P8318, A67P7336 SRAMs integrate a 256K X 18, 128K X 36 SRAM core with advanced synchronous peripheral circuitry and

A43P26161G-75 : 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM

A67P06361E : 2M X 18, 1M X 36 Lvttl, Pipelined ZeBL SRAM

A63L8336E-2.6 : 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output

A67L16181E : 2M X 18, 1M X 36 Lvttl, Pipelined ZeBL SRAM

 
0-C     D-L     M-R     S-Z