Details, datasheet, quote on part number: A63G7332E-45
PartA63G7332E-45
CategoryLogic => Counters
Description128k X 32 Bit Synchronous High Speed SRAM With Burst Counter And Pipelined Data Output
CompanyAMIC Technology Corporation
DatasheetDownload A63G7332E-45 datasheet
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Features, Applications
X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output
X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Revision History

Initial issue Change pin 14 description from VCC to NC Change package type from 100-pin TQFP to 100-pin LQFP Change fast access times from 4.2/4.5/5.0 ns Modify 100-pin LQFP symbol y dimensions Max. 0.08 0.1 Max. in inches 0.003 0.004

X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output
Features

Fast access times: ns (143/133/100 MHZ) Single or +3.3V-5% power supply Separate +2.5V+0.4V/-0.12V isolated output buffer 3.3V tolerant inputs Synchronous burst function Individual Byte Write control and Global Write

n Registered output for pipelined applications n Three separate chip enables allow wide range of options for CE control, address pipelining n Selectable BURST mode n SLEEP mode (ZZ pin) provided n Available in 100-pin LQFP package

The is a high-speed, low-power SRAM containing 4,194,304 bits of bit synchronous memory, organized as 131,072 words by 32 bits. The A63G7332 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output registers and X 32 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 A16), all data inputs - I/O32), active LOW chip enable ( CE two additional chip enables (CE2, CE2 burst control inputs ( ADSC , ADSP , ADV byte write enables ( BWE BW4 ) and Global Write ( GW Asynchronous inputs include output enable ( OE clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). Burst operations can be initiated with either the address status processor ( ADSP ) or address status controller ( ADSC ) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63G7332 and controlled by the burst advance ( ADV ) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK). This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O8, BW2 controls I/O16, BW3 controls - I/O24, and BW4 controls - I/O32, all on the condition that BWE is LOW. GW LOW causes all bytes to be written.


I/O17 I/O18 VCCQ GNDQ I/O21 I/O22 GNDQ VCCQ I/O24 NC VCC NC GND I/O25 I/O26 VCCQ GNDQ I/O29 I/O30 GNDQ VCCQ I/O32 NC

I/O16 I/O15 VCCQ GNDQ I/O12 I/O11 GNDQ VCCQ I/O10 I/O9 GND NC VCC I/O8 I/O7 VCCQ GNDQ I/O4 I/O3 GNDQ VCCQ I/O1 NC


 

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