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Part: A67L0618E-3.8
Category:
Memory
-> SRAM
-> 2 Mb
Description: 1M X 18, 512K X 36 LVTTL, Pipelined ZeBLTM SRAM<<<>>>The AMIC Zero Bus Latency (ZeBLTM) SRAM family<<<>>>employs high-speed, low-power CMOS designs using an<<<>>>advanced CMOS process.<<<>>>The A67L0618, A67L9336 SRAMs integrate a 1M X 18,<<<>>>512K X 36 SRAM core with advanced synchronous<<<>>>peripheral circuitry and a 2-bit burst counter. These SRAMs<<<>>>are optimized for 100 percent bus utilization without the<<<>>>insertion of any wait cycles during Write-Read alternation.<<<>>>The positive edge triggered single clock input (CLK) controls<<<>>>all synchronous inputs passing through the registers. The<<<>>>synchronous inputs include all address, all data inputs,<<<>>>active low chip enable (CE), two additional chip enables for<<<>>>easy depth expansion (CE2, CE2 ), cycle start input<<<>>>(ADV/ LD ), synchronous clock enable ( CEN), byte write<<<>>>enables (BW1,BW2,BW3,BW4) and read/write (R/W).<<<>>>Asynchronous inputs include the output enable (OE), clock<<<>>>(CLK), SLEEP mode (ZZ, tied LOW if unused) and burst<<<>>>mode (MODE). Burst Mode can provide either interleaved or<<<>>>linear operation, burst operation can be initiated by<<<>>>synchronous address Advance/Load (ADV/LD) pin in Low<<<>>>state. Subsequent burst address can be internally<<<>>>generated by the chip and controlled by the same input pin<<<>>>ADV/LD in High state
Company: AMIC Technology Corporation
Datasheet: Download A67L0618E-3.8 datasheet File size : 258 kB
Request For quote: Find where to buy A67L0618E-3.8
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