|Category||Memory => SRAM|
|Description||256k X 16/18, 128k X 32/36 Lvttl, Pipelined Dba SRAM|
|Company||AMIC Technology Corporation|
|Datasheet||Download A67L7332E-45 datasheet
|Document Title X 32/36 LVTTL, Pipelined DBA SRAM Revision History
Initial issue Change fast access time from 4.5/5.0/6.0 ns
n Fast access time: (117/100/83MHz) n Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization n Signal ± 5% power supply n Individual Byte Write control capability n Clock enable ( CEN ) pin to enable clock and suspend operations n Clock-controlled and registered address, data and control signals n Registered output for pipelined applications n Three separate chip enables allow wide range of options for CE control, address pipelining n Internally self-timed write cycle n Selectable BURST mode (Linear or Interleaved) n SLEEP mode (ZZ pin) provided n Available in 100 pin LQFP package
The AMIC Direct Bus AlternationTM (DBATM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L7332, A67L7336 SRAMs integrate X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during WriteRead alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable ( CE two additional chip enables for easy depth expansion (CE2, CE2 cycle start input (ADV/LD synchronous clock enable ( CEN byte write enables BW4 ) and read/write (R/ W Asynchronous inputs include the output enable ( OE clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/LD ) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/LD in High state. Write cycles are internally self-time and synchronous with the rising edge of the clock input and when W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4 controls I/Od pins. Cycle types can only be defined when an address is loaded, i.e., when ADV/LD is LOW. Parity/ECC bits are only available on the X18/36 version. The SRAM operates from a +3.3V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems.
I/Oc1 I/Oc2 VCCQ VSSQ I/Oc5 I/Oc6 VSSQ VCCQ I/Oc7 I/Oc8 VCC VSS I/Od0 I/Od1 VCCQ VSSQ I/Od4 I/Od5 VSSQ VCCQ I/Od 6 I/Od 7 I/Od8 /NC
NC VCCQ VSSQ I/Ob0 I/Ob1 VSSQ VCCQ I/Ob2 I/Ob3 VCC VSS I/Ob4 I/Ob5 VCCQ VSSQ I/Ob8/NC NC VSSQ VCCQ NC
A17 NC VCCQ VSSQ I/Oa7 I/Oa6 VSSQ VCCQ I/Oa5 I/Oa4 VSS VCC I/Oa3 I/Oa2 VCCQ VSSQ I/Oa0 NC VSSQ VCCQ NC
I/Ob7 I/Ob6 VCCQ VSSQ I/Ob3 I/Ob2 VSSQ VCCQ I/Ob1 I/Ob0 VSS VCC I/Oa8 I/Oa7 VCCQ VSSQ I/Oa4 I/Oa3 VSSQ VCCQ I/Oa1 I/Oa0/NC
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