Details, datasheet, quote on part number: A67L8318E-4.2
PartA67L8318E-4.2
CategoryMemory => SRAM => 256 Kb
Description256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM
The AMIC Zero Bus Latency (ZeBLTM) SRAM family
employs high-speed, low-power CMOS designs using an
advanced CMOS process.
The A67L8318, A67L7336 SRAMs integrate a 256K X 18,
128K X 36 SRAM core with advanced synchronous
peripheral circuitry and a 2-bit burst counter. These SRAMs
are optimized for 100 percent bus utilization without the
insertion of any wait cycles during Write-Read alternation.
The positive edge triggered single clock input (CLK) controls
all synchronous inputs passing through the registers. The
synchronous inputs include all address, all data inputs,
active low chip enable (CE), two additional chip enables for
easy depth expansion (CE2, CE2 ), cycle start input
(ADV/ LD ), synchronous clock enable ( CEN), byte write
enables (BW1,BW2,BW3,BW4) and read/write (R/W).
Asynchronous inputs include the output enable (OE), clock
(CLK), SLEEP mode (ZZ, tied LOW if unused) and burst
mode (MODE). Burst Mode can provide either interleaved or
linear operation, burst operation can be initiated by
synchronous address Advance/Load (ADV/LD) pin in Low
state. Subsequent burst address can be internally
generated by the chip and controlled by the same input pin
ADV/LD in High state.
CompanyAMIC Technology Corporation
DatasheetDownload A67L8318E-4.2 datasheet
PackagesLQFP
  

 

Features, Applications
Document Title X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History
Initial issue Modify DC specification to exact value
Features

Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined applications Three separate chip enables allow wide range of options for CE control, address pipelining Internally self-timed write cycle Selectable BURST mode (Linear or Interleaved) SLEEP mode (ZZ pin) provided Available in 100 pin LQFP package

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L8318, A67L7336 SRAMs integrate X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable ( CE two additional chip enables for easy depth expansion (CE2, CE2 cycle start input (ADV/ LD synchronous clock enable ( CEN byte write enables BW4 ) and read/write (R/ W Asynchronous inputs include the output enable ( OE clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/ LD ) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/ LD in High state. Write cycles are internally self-time and synchronous with the rising edge of the clock input and when W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4 controls I/Od pins. Cycle types can only be defined when an address is loaded. The SRAM operates from a +3.3V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems.


I/Oc0 I/Oc1 VCCQ VSSQ I/Oc4 I/Oc5 VSSQ VCCQ I/Oc6 I/Oc7 VCC VSS I/Od0 I/Od1 VCCQ VSSQ I/Od4 I/Od5 VSSQ VCCQ I/Od7 I/Od8

NC VCCQ VSSQ I/Ob8 I/Ob7 VSSQ VCCQ I/Ob6 I/Ob5 VCC VSS I/Ob4 I/Ob3 VCCQ VSSQ I/Ob0 NC VSSQ VCCQ NC

A10 NC VCCQ VSSQ I/Oa1 I/Oa2 VSSQ VCCQ I/Oa3 I/Oa4 VSS VCC I/Oa5 I/Oa6 VCCQ VSSQ I/Oa8 NC VSSQ VCCQ NC

I/Ob7 I/Ob6 VCCQ VSSQ I/Ob3 I/Ob2 VSSQ VCCQ I/Ob1 I/Ob0 VSS VCC I/Oa7 I/Oa6 VCCQ VSSQ I/Oa3 I/Oa2 VSSQ VCCQ I/Oa0 I/Oa8



 

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