|
|
Part: AP160
Category:
Memory
-> ROM
-> OTP ROM
Description: 8-bit Microcontroller With 8kb Otp
Company: AMIC Technology Corporation
Datasheet: Download AP160 datasheet File size : 174 kB
Request For quote: Find where to buy AP160
Datasheet text preview:
AP160 8-BIT MICROCONTROLLER WITH 8KB OTP
GENERAL DESCRIPTION
The AP160 is a wide operating voltage, Low power consumption and high performance with AMIC high-density CMOS technology. All instruction set of AP160 are fully compatible with the standard 8051. The AP160 contains 8K bytes OTP EPROM, 256 bytes RAM, four 8-bit bi-directional and bit addressable I/O ports, three 16-bit timer/counter and eight interrupt sources. To reduce power consumption, idle mode and power down mode are provided to implementation. For data protection, program lock bits can be performed through programming LB1, LB2 and LB3. The AMIC AP160 is a useful and powerful microcontroller in many control system application.
DATA SHEET
October 2001
FEATURES
l l l l l l l l l l l l l
Compatible with MCS-51 Products 256 X 8 bit internal Data RAM. 8KB On-Chip OTP EPROM. 2.7V~5.5V Operating Range. Fully Static Operation : 0Hz to 16 MHz 0~33MHZ speed range at VCC=5V. 32 Programmable I/O pins Three 16-Bit Timers/Counters. Programmable clock out. Full-duplex UART Eight interrupt sources. 2 level priority-interrupt. Power reduction control modes
n n
Idle mode Power-down mode
l l l l
3 security bits. Low EMI (Inhibit ALE) Wake-up from Power Down by an external interrupt. Available in PLCC and QFP44 packages.
Version 0.0
1
AMIC Technology, Inc.
AP160
PIN CONFIGURATIONS
n PLCC
P1.1 (T2EX)
P0.0 (AD0)
P0.1 (AD1) 42
P0.2 (AD2) 41
6
5
4
3
2
1
44
43
40 39 38 37 36 35 34 33 32 31 30 29
P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
P0.3 (AD3)
P1.0 (T2)
NC VCC
P1.4
P1.3
P1.2
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
AP160L
(WR) P3.6
(RD) P3.7 XTAL2
XTAL1
GND NC
(A8) P2.0
(A9) P2.1 P0.0 (AD0)
(A10) P2.2 P0.1 (AD1) 36
n QFP
P1.1 (T2EX)
P0.2 (AD2) 35
44
43
42
41
40
39
38
37
P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
34 33 32 31 30 29 28 27 26 25 24 23
P0.3 (AD3)
P1.0 (T2)
NC VCC
P1.4
P1.3
P1.2
(A11) P2.3 (A12) P2.4
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
AP160F
(WR) P3.6
(RD) P3.7 XTAL2
XTAL1
GND GND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3 (A12) P2.4
Version 0.0
2
AMIC Technology, Inc.
AP160
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
VCC GND
PORT 0 DRIVERS
PORT 2 DRIVERS
RAM ADDR. REGISTER
RAM
PORT0 LATACH
PORT2 LATACH
QUICK FLASH
B REGISTER
ACC
STACK POINTER
PROGRAM ADDRESS REGISTER
TMP2
TMP1
BUFFER
ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW
PC INCREMENTER
PROGRAM COUNER
PSEN
ALE/ PROG EA /VPP RST
TIMING AND CONTROL
INSTRUCTION REGISTER
DPTR
PORT1 LATACH
PORT3 LATACH
OSC
PORT 1 DRIVERS
PORT 3 DRIVERS
P1.0-P1.7
P3.0-P3.7
Version 0.0
3
AMIC Technology, Inc.
AP160
PIN DESCRIPTIONS
SYMBOL VSS VCC P0.0-P0.7 TYPE I I I/O Ground. Supply voltage. Port 0 is an 8-bit open drain, bidirectional I/O port. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups. Port 0 also receives the code bytes during programming on-chip OTP EPROM and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current ( IIL ) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following: T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out) T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control. Port 1 also receives the low-order address bytes during programming on-chip OTP EPROM and verification. P2.0-P2.7 I/O Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current ( IIL ) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during programming on-chip OTP EPROM and verification. Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current ( IIL ) because of the pullups. Port 3 also serves the functions of various special features of the AP160, as shown below: RXD (P3.0): Serial input port TXD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Port 3 also receives some control signals for programming and verification. RST I Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. DESCRIPTIONS
P1.0-P1.7
I/O
P3.0-P3.7
I/O
Version 0.0
4
AMIC Technology, Inc.
AP160
SYMBOL ALE/PROG TYPE O/I DESCRIPTIONS Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Programming on-chip OPT EPROM. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. Program Store Enable is the read strobe to external program memory. When the AP160 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during programming OTP EPROM. Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier.
PSEN
O
EA/Vpp
I
XTAL1 XTAL2
I O
Version 0.0
5
AMIC Technology, Inc.
Others parts begin by ap
AP-1 AP-2 AP-3 AP-4 AP-5 AP-6 AP-7 AP-8 AP-9 AP-10 AP-11 AP-12 AP-13 AP-14 AP-15
|
|
|
