Details, datasheet, quote on part number: FQV2105
PartFQV2105
CategoryMemory => FIFO => 256 Kb
Description3.3 Volt Synchronous x18 First-In/First-Out Queue
HBAs FlexQ II offers industry leading FIFO queuing bandwidth (up to 3.0 Gbps), with a wide range of memory
configurations (from 8,192 x 18 to 262,144 x 18). System designer has full flexibility of implementing deeper and wider queues
using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between
transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation
of virtual queue depths.
CompanyAMIC Technology Corporation
DatasheetDownload FQV2105 datasheet
  

 

Features, Applications

Industry leading First-In/First-Out Queues (up to 133MHz) Write cycle time of 7.5ns independent of Read cycle time Read cycle time of 7.5ns independent of Write cycle time 3.3V power supply 5V input tolerant on all control and data input pins 5V output tolerant on all flags and data output pins Master Reset clears all previously programmed configurations including Write and Read pointers Partial Reset clears Write and Read pointers but maintains all previously programmed configurations First Word Fall Through (FWFT) and Standard Timing modes Presets for eight different Almost Full and Almost Empty offset values Parallel/Serial programming of PRAF and PRAE offset values Full, Empty, Almost Full, Almost Empty, and Half Full indicators Asynchronous output enable tri-state data output drivers Data retransmission Available package: 64 - pin Plastic Thin Quad Flat Pack (TQFP), 64 - pin Slim Thin Quad Flat Pack (STQFP) to 70C) Commercial operating temperature available for cycle time of 7.5ns and above to 85C) Industrial operating temperature available for cycle time of 7.5ns and above

HBA's FlexQTM II offers industry leading FIFO queuing bandwidth (up to 3.0 Gbps), with a wide range of memory configurations (from x 18). System designer has full flexibility of implementing deeper and wider queues using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation of virtual queue depths. 5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching capability. Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will initialize Write and Read pointers to zero. In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high transition of RCLK. Subsequent reads from the queue will require asserting REN. This feature is useful when implementing depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively. In Standard mode, always assert REN for read operation. FULL and EMPTY are used instead of DRDY and QRDY respectively.

PRAF , PRAE , and HALF are available in either FWFT or Standard mode.

2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.

At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. Both zero and normal latency timing modes are available for retransmit operation. These FlexQTM II devices have low power consumption, hence minimizing system power requirements. In addition, industry standard 64 - pin Plastic TQFP and 64 - pin STQFP are offered to save system board space. These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc.

WRITE CLOCK (WCLK) WRITE ENABLE (WEN) LOAD ( LOAD) x18 DATA - 0) SERIAL DATA ENABLE (SDEN) FIRST WORD FALL THROUGH/ SERIAL DATA INPUT (FWFT/SDI) FULL FLAG / INPUT READY ( FULL / DRDY) PROGRAMMABLE ALMOST-FULL (PRAF FQV265 FQV255

READ CLOCK (RCLK) READ ENABLE (REN ) OUTPUT ENABLE (OE) x18 DATA OUT - 0) RETRANSMIT ( RET ) EMPTY FLAG / OUTPUT READY ( EMPTY/ QRDY ) PROGRAMMABLE ALMOSTEMPTY ( PRAE ) HALF-FULL FLAG (HALF )

Figure 1. Single Device Configuration Signal Flow Diagram

2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.

2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.


 

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