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Part: 5962-0053001HXA
Category:
Multimedia
-> Video
-> A/D Converters
Description: Dual Channel, 12-bit, 80 MSPS A/D Converter With Analog Input Signal Conditioning
Company: Analog Devices
Datasheet: Download 5962-0053001HXA datasheet File size : 134 kB
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Dual Channel, 12-Bit, 80 MSPS A/D Converter with Analog Input Signal Conditioning AD13280
and performance while still maintaining excellent isolation, and providing for significant board area savings. Multiple options are provided for driving the analog input, including single-ended, differential, and optional series filtering. The AD13280 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while still remaining general purpose. The AD13280 operates with ± 5.0 V for the analog signal conditioning with a separate 5.0 V supply for the analog-to-digital conversion, and 3.3 V digital supply for the output stage. Each channel is completely independent allowing operation with independent encode and analog inputs, and maintaining minimal crosstalk and interference. The AD13280 is packaged in a 68-lead ceramic gull wing package. Manufacturing is done on Analog Devices, Inc. MIL-38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (40°C to +85°C). The components are manufactured using Analog Devices, Inc. high-speed complementary bipolar process (XFCB).
PRODUCT HIGHLIGHTS
FEATURES Dual, 80 MSPS Minimum Sample Rate Channel-to-Channel Matching, 1% Gain Error 90 dB Channel-to-Channel Isolation DC-Coupled Signal Conditioning 80 dB Spurious-Free Dynamic Range Selectable Bipolar Inputs ( 1 V and 0.5 V Ranges) Integral Single-Pole Low-Pass Nyquist Filter Two's Complement Output Format 3.3 V Compatible Outputs 1.85 W per Channel Industrial and Military Grade APPLICATIONS Radar Processing (Optimized for I/Q Baseband Operation) Phased Array Receivers Multichannel, Multimode Receivers GPS Antijamming Receivers Communications Receivers PRODUCT DESCRIPTION
The AD13280 is a complete dual channel signal processing solution including on board amplifiers, references, ADCs, and output termination components to provide optimized system performance. The AD13280 has on-chip track-and-hold circuitry and utilizes an innovative multipass architecture to achieve 12-bit, 80 MSPS performance. The AD13280 uses innovative highdensity circuit design and laser-trimmed thin-film resistor networks to achieve exceptional channel matching, impedance control,
1. Guaranteed sample rate of 80 MSPS. 2. Input signal conditioning included; gain and impedance match. 3. Single-ended, differential, or off-module filter options. 4. Fully tested/characterized full channel performance. 5. Compatible with 14-bit (up to) 65 MSPS family.
FUNCTIONAL BLOCK DIAGRAM
AMP-IN-A-2 AMP-IN-A-1 AMP-IN-B-2 AMP-IN-B-1
AMP-OUT-A AIN A+IN DROUTA (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A TIMING 9 VREF DROUT 12 100 OUTPUT TERMINATORS 3 100 VREF DROUT 12 OUTPUT TERMINATORS 7 5
AMP-OUT-B
AD13280
B+IN BIN
DROUTB ENC TIMING ENC D11B (MSB) D10B D9B D8B D7B D9A D10A D11A (MSB) D0B D1B D2B D3B D4B D5B (LSB) D6B
ENC ENC
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD13280SPECIFICATIONS
Parameter RESOLUTION DC ACCURACY No Missing Codes Offset Error Offset Error Channel Match Gain Error2 Gain Error Channel Match
1
(AVCC = +5 V, AVEE = 5 V, DVCC = +3.3 V; applies to each ADC with Front-End Amplifier unless otherwise noted.)
Temp Test Level Mil Subgroup Min AD13280AZ/BZ Typ Max 12 Full 25° C Full Full 25° C Full 25° C Max Min IV I VI VI I VI I VI VI 12 1 2, 3 1, 2, 3 1 2, 3 1 2 3 Guaranteed ± 1.0 ± 1.0 ± 0.1 1.0 ± 2.0 ± 0.5 ± 1.0 ± 1.0 Unit Bits
2.2 2.2 1.0 3 5.0 1.5 3.0 5
+2.2 +2.2 +1.0 +1 +5.0 +1.5 +3.0 +5
% FS % FS % % FS % FS % % %
SINGLE-ENDED ANALOG INPUT Input Voltage Range AMP-IN-X-1 AMP-IN-X-2 Input Resistance AMP-IN-X-1 AMP-IN-X-2 Capacitance Analog Input Bandwidth3 DIFFERENTIAL ANALOG INPUT Analog Signal Input Range A+IN to AIN and B+IN to BIN 4 Input Impedance Analog Input Bandwidth ENCODE INPUT (ENC, ENC)1 Differential Input Voltage Differential Input Resistance Differential Input Capacitance SWITCHING PERFORMANCE Maximum Conversion Rate 5 Minimum Conversion Rate 5 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulsewidth High at Max Conversion Rate ENCODE Pulsewidth Low at Max Conversion Rate Output Delay (tOD) Encode, Rising to Data Ready, Rising Delay S N R 1, 6 Analog Input @ 10 MHz
Full Full Full Full 2 5° C Full
V V IV IV V V 12 12 99 198
± 0.5 ± 1.0 100 200 4.0 100 101 202 7.0
V V pF MHz
Full 2 5° C Full Full 2 5° C 2 5° C Full Full 25° C 25° C 2 5° C 2 5° C 25° C Full Full 25° C Min Max 25° C Min Max 25° C Min Max 25° C Min Max 25° C Min Max 25° C Min Max
V V V IV V V VI IV V IV V IV IV V V I II II I II II I II II I II II I II II I II II 12 0.4
±1 618 50
V MHz V p-p k pF MSPS MSPS ns ps ps rms ns ns ns ns dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
10 2.5 4, 5, 6 12 12 12 12 4.75 4.75 80 20 1.5 250 0.3 6.25 6.25 5 8.5 70 500 8 8
Analog Input @ 21 MHz
Analog Input @ 37 MHz
4 6 5 4 6 5 4 6 5 4 6 5 4 6 5 4 6 5
67.5 64.5 67.5 67.5 64 67.5 63.5 61.5 63.5 67 63.5 67 65 63 65 54.5 53 54.5
70
65
S I N A D 1, 7 Analog Input @ 10 MHz
69
Analog Input @ 21 MHz
68.5
Analog Input @ 37 MHz
59
2
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AD13280
Parameter SPURIOUS-FREE DYNAMIC RANGE Analog Input @ 10 MHz
1, 8
Temp 25° C Min Max 25° C Min Max 25° C Min Max 25° C 25° C 25° C 25° C 2 5° C Min Max 2 5° C 2 5° C 25° C 2 5° C
Test Level I II II I II II I II II V V V V I II II V V IV V
Mil Subgroup 4 6 5 4 6 5 4 6 5
Min 75 70 75 68 67 68 56 55 56
AD13280AZ/BZ Typ Max 80
Unit dBFS
Analog Input @ 21 MHz
75
dBFS
Analog Input @ 37 MHz
62
dBFS
SINGLE-ENDED ANALOG INPUT Passband Ripple to 10 MHz Passband Ripple to 25 MHz DIFFERENTIAL ANALOG INPUT Passband Ripple to 10 MHz Passband Ripple to 25 MHz TWO-TONE IMD REJECTION 9 fIN = 9.1 MHz and 10.1 MHz f1 and f2 are 7 dB fIN = 19.1 MHz and 20.7 MHz f1 and f2 are 7 dB fIN = 36 MHz and 37 MHz f1 and f2 are 7 dB CHANNEL-TO-CHANNEL ISOLATION 10 TRANSIENT RESPONSE DIGITAL OUTPUTS11 Logic Compatibility DVCC = 3.3 V Logic "1" Voltage Logic "0" Voltage DVCC = 5 V Logic "1" Voltage Logic "0" Voltage Output Coding POWER SUPPLY AVCC Supply Voltage12 I (AVCC) Current AVEE Supply Voltage12 I (AVEE) Current DVCC Supply Voltage12 I (DVCC) Current ICC (Total) Supply Current per Channel Power Dissipation (Total) Power Supply Rejection Ratio (PSRR)
0.05 0.1 0.3 0.82 4 6 5 4 4 12 90 25 CMOS 75 71 75 80
dB dB dB dB dBc
77 60
dBc dBc dB ns
Full Full Full Full
I I V V
1, 2, 3 1, 2, 3
2.5
DVCC 0.2 0.2 0.5 DVCC 0.3 0.35 Two's Complement
V V V V
Full Full Full Full Full Full Full Full Full
IV I IV I IV I I I V
4.85 1, 2, 3 5.25 1, 2, 3 3.135 1, 2, 3 1, 2, 3 1, 2, 3
5.0 310 5.0 38 3.3 34 369 3.72 0.01
5.25 338 4.75 49 3.465 46 433 4.05
V mA V mA V mA mA W % FSR/% VS
NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially. Single-ended input: AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND. 2 Gain tests are performed on AMP-IN-X-1 input voltage range. 3 Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 For differential input: +IN = 1 V p-p and IN = 1 V p-p (signals are 180 ° out of phase). For single-ended input: +IN = 2 V p-p and = IN = GND. 5 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 6 Analog Input signal power at 1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR is reported in dBFS, related back to converter full scale. 7 Analog Input signal power at 1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is reported in dBFS, related back to converter full scale. 8 Analog Input signal at 1 dBFS; SFDR is ratio of converter full scale to worst spur. 9 Both input tones at 7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. 10 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B Channel. 11 Digital output logic levels: DV CC = 3.3 V, C LOAD = 10 pF. Capacitive loads > 10 pF will degrade performance. 12 Supply voltage recommended operating range. AV CC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. Specifications subject to change without notice.
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AD13280
ABSOLUTE MAXIMUM RATINGS
E L E C T R I C A L1 AVCC Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V AVEE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V to 0 V DVCC Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . VEE to VCC Analog Input Current . . . . . . . . . . . . . . 10 mA to +10 mA Digital Input Voltage (ENCODE) . . . . . . . . . . . . . 0 to VCC ENCODE, ENCODE Differential Voltage . . . . . . . . 4 V max Digital Output Current . . . . . . . . . . . . . . 10 mA to +10 mA ENVIRONMENTAL2 Operating Temperature (Case) . . . . . . . . . 40°C to +85°C Maximum Junction Temperature . . . . . . . . . . . . . . . . 175°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C Storage Temperature Range (Ambient) . . 65°C to +150°C
NOTES 1 Absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedance for "ES" package: JC 2.2°C/W; JA 24.3°C/W.
PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier (ES-68C)
AMP-OUT-A A+IN B+IN AMP-OUT-B AMP-IN-A-2 AMP-IN-A-1 AMP-IN-B-1 AMP-IN-B-2
SHIELD AGNDB
AGNDA
AIN AGNDA
AGNDA
AGNDB
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 PIN 1 IDENTIFIER 60 AGNDB 59 A V E EB 58 A V C CB 57 AGNDB 56 ENCODEB 55 ENCODEB 54 AGNDB
AGNDA 10 A V E EA 11 A V C CA 12 AGNDA 13 ENCODEA 14 ENCODEA 15 AGNDA 16 D V C CA 17 NC 18 NC 19 D0A(LSB) 20 D1A 21 D2A 22 D3A 23 D4A 24 D5A 25 DGNDA 26
AD13280
TOP VIEW (Not to Scale)
AGNDB
53 D V C CB 52 D11B(MSB) 51 D10B 50 D9B 49 D8B 48 D7B 47 D6B 46 D5B 45 D4B 44 DGNDB
TEST LEVEL
I
100% Production Tested.
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DROUTB NC NC
BIN
D1B D2B
D3B
D10A D11A(MSB)
SHIELD
II 100% Production Tested at 25°C, and sample tested at specified temperatures. AC testing done on sample basis. III Sample Tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested with temperature at 25°C: sample tested at temperature extremes.
ORDERING GUIDE
NC = NO CONNECT
Model AD13280AZ AD13280AF 5962-0053001HXA AD13280/PCB
Temperature Range (Case) 25°C to +85°C 25°C to +85°C 40°C to +85°C 25 °C
Package Description 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar 68-Lead Ceramic Leaded Chip Carrier Evaluation Board with AD13280AZ
D0B(LSB)
DROUTA
DGNDA
Package Option ES-68C ES-68C ES-68C
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD13280 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4
DGNDB
D6A
D7A D8A D9A
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AD13280
PIN FUNCTION DESCRIPTIONS
Pin No. 1, 35 2, 3, 9, 10, 13, 16 4 5 6 7 8 11 12 14 15 17 18, 19, 37, 38 2025, 2833 26, 27 34 36 3942, 4552 43, 44 53 54, 57, 60, 61, 67, 68 55 56 58 59 62 63 64 65 66
Name SHIELD AGNDA AIN A+IN AMP-OUT-A AMP-IN-A-1 AMP-IN-A-2 AV EEA A V C CA ENCODEA ENCODEA D V C CA NC D0AD11A DGNDA DROUTA DROUTB D0BD11B DGNDB D V C CB AGNDB ENCODEB ENCODEB A V C CB AV EEB AMP-IN-B-2 AMP-IN-B-1 AMP-OUT-B B+IN BIN
Function Internal Ground Shield between Channels A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Inverting Differential Input (Gain = 1). Noninverting Differential Input (Gain = 1). Single-Ended Amplifier Output (Gain = 2). Analog Input for A Side ADC (Nominally ± 0.5 V). Analog Input for A Side ADC (Nominally ± 1.0 V). A Channel Analog Negative Supply Voltage (Nominally 5.0 V or 5.2 V). A Channel Analog Positive Supply Voltage (Nominally 5.0 V). Complement of Encode; Differential Input. Encode Input; Conversion Initiated on Rising Edge. A Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V). No Connect. Digital Outputs for ADC A. D0 (LSB). A Channel Digital Ground. Data Ready A Output. Data Ready B Output. Digital Outputs for ADC B. D0 (LSB). B Channel Digital Ground. B Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V). B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Encode Input; Conversion Initiated on Rising Edge. Complement of Encode; Differential Input. B Channel Analog Positive Supply Voltage (Nominally 5.0 V). B Channel Analog Negative Supply Voltage (Nominally 5.0 V or 5.2 V). Analog Input for B Side ADC (Nominally ± 1.0 V). Analog Input for B Side ADC (Nominally ± 0.5 V). Single-Ended Amplifier Output (Gain = 2). Noninverting Differential Input (Gain = 1). Inverting Differential Input (Gain = 1).
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