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Part: 5962-0150601HXA
Category:
Multimedia
-> Video
-> A/D Converters
Description: Dual Channel, 14-bit, 65 MSPS A/D Converter With Analog Input Signal Conditioning
Company: Analog Devices
Datasheet: Download 5962-0150601HXA datasheet File size : 134 kB
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Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning AD13465
state-of-the-art high-density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional channel matching and impedance control, and provide for significant board area savings. Multiple options are provided for driving the analog input, including single-ended, differential, and optional series filtering. The AD13465 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while remaining general-purpose. The AD13465 operates with ± 5.0 V for the analog signal conditioning, 5.0 V supply for the analog-to-digital conversion, and 3.3 V digital supply for the output stage. Each channel is completely independent, allowing operation with independent Encode and Analog Inputs, while maintaining minimal crosstalk and interference. Th e AD13465 is packaged in a 68-lead ceramic gull wing p a c k a g e . Manufacturing is done on Analog Devices' MIL38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (40°C to +85°C). The components are manufactured using Analog Devices' high-speed complementary bipolar process (XFCB).
PRODUCT HIGHLIGHTS
FEATURES Dual, 65 MSPS Minimum Sample Rate Channel-to-Channel Matching, 1% Gain Error 90 dB Channel-to-Channel Isolation DC-Coupled Signal Conditioning 85 dB Spurious-Free Dynamic Range Selectable Bipolar Inputs ( 1 V and 0.5 V Ranges) Integral Two-Pole Low-Pass Nyquist Filter Two's Complement Output Format 3.3 V Compatible Outputs 1.8 W per Channel Industrial and Military Grade APPLICATIONS Radar Processing Optimized for I/Q Baseband Operation Phased Array Receivers Multichannel, Multimode Receivers GPS Antijamming Receivers Communications Receivers PRODUCT DESCRIPTION
The AD13465 is a complete dual channel signal processing solution including on-board amplifiers, references, ADCs, and output termination components to provide optimized system performance. The AD13465 has on-chip track-and-hold circuitry and utilizes an innovative multipass architecture to achieve 14-bit, 65 MSPS performance. The AD13465 uses
1. Guaranteed sample rate of 65 MSPS. 2. Input signal conditioning included; gain and impedance matching. 3. Single-ended, differential, or off-module filter options. 4. Fully tested/characterized full channel performance 5. Pin compatible with 12-bit AD13280 product family.
AMP-IN-B-2 AMP-IN-B-1
FUNCTIONAL BLOCK DIAGRAM
AMP-IN-A-2 AMP-IN-A-1
AMP-OUT-A AIN A+IN DROUTA (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A 11 100 TIMING VREF DROUT 14 OUTPUT TERMINATORS 3 100 OUTPUT TERMINATORS 9 VREF DROUT 14 5
AMP-OUT-B B+IN BIN
AD13465
TIMING
DROUTB ENC ENC
D13B (MSB) D12B D11B D10B D9B
REV. 0
ENC ENC
D11A D12A D13A (MSB)
D0B D1B D2B D3B D4B D5B (LSB)
D6B D7B D8B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD13465TARGET SPECIFICATIONS End Amplifier unless otherwise noted.)
Parameter RESOLUTION Temp Test Level Mil SubGroup Min 14
(AVCC = 5 V; AVEE = 5 V; DVCC = 3.3 V applies to each ADC with Front
AD13465AZ/BZ Typ Max
Unit Bits
DC ACCURACY No Missing Codes Offset Error Offset Error Channel Match Gain Error1 Gain Error Channel Match
Full 25 °C Full Full 25 °C Full 25 °C Max Min
IV I VI VI I VI I VI VI
12 1 2, 3 1, 2, 3 1 2, 3 1 2 3
2.2 2.2 1.0 3.0 5.0 +1.5 3.0 5.0
Guaranteed ± 0.2 ± 1.0 ± 0.1 1.0 ± 2.0 ± 0.5 ± 1.0 ± 1.0
+2.2 +2.2 +1.0 +1.0 +5.0 +1.5 +3.0 +5.0
% FS % FS % FS % FS % FS % FS % FS % FS
SINGLE-ENDED ANALOG INPUT Input Voltage Range AMP-IN-X-1 AMP-IN-X-2 Input Resistance AMP-IN-X-1 AMP-IN-X-2 Input Capacitance2 Analog Input Bandwidth 3 DIFFERENTIAL ANALOG INPUT Analog Signal Input Range A+IN to AIN and B+IN to BIN 4 Input Impedance Analog Input Bandwidth 3 ENCODE INPUT (ENC, ENC) 5 Differential Input Voltage Differential Input Resistance Differential Input Capacitance SWITCHING PERFORMANCE Maximum Conversion Rate 6 Minimum Conversion Rate 6 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulse with High ENCODE Pulse with Low Output Delay (tOD) Encode, Rising to Data Ready, Rising Delay SNR7 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 21 MHz Analog Input @ 32 MHz SINAD 8 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 21 MHz Analog Input @ 32 MHz
Full Full Full Full Full
V V IV IV V 12 12 99 198
± 0.5 ± 1.0 100 200 4.0 100 101 202 7.0
V V pF MHz
Full Full Full Full 2 5 °C 2 5 °C Full Full 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C Full Full
V V V IV V V VI IV V IV V IV IV IV V 12 0.4
± 1.0 618 50
V MHz V p-p k pF MSPS MSPS ns ps ps rms ns ns ns ns
10 2.5 4, 5, 6 12 12 12 12 12 5.0 5.0 65 20 1.5 250 0.3 7.7 7.7 7.5 11.5 500 9.5 9.5
2 5 °C 2 5 °C Full 2 5 °C Full 2 5 °C Full 2 5 °C 2 5 °C Full 2 5 °C Full 2 5 °C Full
V I II I II V V V I II I II V V
4 5, 6 4 5, 6
70 69 69 68
72 72 71 71 70 70 69 72 72 70.5 70 69 63 61
dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
4 5, 6 4 5, 6
69 68.5 66.5 66
2
REV. 0
AD13465
Parameter SPURIOUS-FREE DYNAMIC RANGE Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 21 MHz Analog Input @ 32 MHz SINGLE-ENDED ANALOG INPUT Pass Band Ripple to 10 MHz Pass Band Ripple to 25 MHz DIFFERENTIAL ANALOG INPUT Pass Band Ripple to 10 MHz Pass Band Ripple to 25 MHz TWO-TONE IMD REJECTION 10 fIN = 9.1 MHz and 10.1 MHz f1 and f2 are 7 dB fIN = 19.1 MHz and 20.7 MHz f1 and f2 are 7 dB CHANNEL-TO-CHANNEL ISOLATION 11 TRANSIENT RESPONSE DIGITAL OUTPUTS Logic Compatibility DVCC = 3.3 V Logic 1 Voltage Logic 0 Voltage D V CC = 5 V Logic 1 Voltage Logic 0 Voltage Output Coding
12 9
Temp 2 5 °C 2 5 °C Full 2 5 °C Full 2 5 °C Full 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C Full 2 5 °C 2 5 °C 2 5 °C
Test Level V I II I II V V V V V V I II V IV V
Mil SubGroup
Min
AD13465AZ/BZ Typ Max 85 86 84 76 74 63 62 0.05 0.1 0.3 0.82
U nit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dB dB dB dB dBc dBc dB
4 5, 6 4 5, 6
80 78 70 69
4 5, 6
77.5 76.5
82 80 72
12
90 15.3 CMOS
ns
Full Full Full Full
I I V V
1, 2, 3 1, 2, 3
2.5
DVCC 0.2 0.2 0.5 DVCC 0.3 0.35 Two's Complement
V V V V
POWER SUPPLY AVCC Supply Voltage13 I (AVCC) Current AVEE Supply Voltage13 I (AVEE) Current DVCC Supply Voltage13 I (DVCC) Current (Total) Supply Current per Channel Power Dissipation (Total) Power Supply Rejection Ratio (PSRR)
Full Full Full Full Full Full Full Full Full
VI V VI V VI V I I V
4.85 5.25 3.135 1, 2, 3 1, 2, 3
5.0 270 5.0 38 3.3 34 369 3.57 0.02
5.25 308 4.75 49 3.465 46 403 3.9
V mA V mA V mA mA W % FSR/ % VS
NOTES 1 Gain tests are performed on AMP-IN-X-1 input voltage range. 2 Input capacitance spec. combines AD8037 capacitance and ceramic package capacitance. 3 Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 For differential input: +IN = 1 V p-p and IN = 1 V p-p (signals are 180 ° out of phase). For single ended input: +IN = 2 V p-p and IN = GND. 5 All AC specifications tested by driving ENCODE and ENCODE differentially. AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND. 6 Minimum and Maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 7 Analog Input signal power at 1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR is reported in dBFS, related back to converter full scale. 8 Analog Input signal power at 1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. SINAD is reported in dBFS, related back to converter full scale. 9 Analog Input signal power at 1 dBFS; SFDR is ratio of converter full scale to worst spur. 10 Both input tones at 7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. 11 Channel-to-channel isolation tested with A Channel grounded and a full-scale signal applied to B Channel. 12 Digital output logic levels: DV CC = 3.3 V, C LOAD = 10 pF. Capacitive loads > 10 pF will degrade performance. 13 Supply voltage recommended operating range. AV CC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. Specifications subject to change without notice.
REV. 0
3
AD13465
ABSOLUTE MAXIMUM RATINGS 1 TEST LEVEL
ELECTRICAL AVCC Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V AVEE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V to 0 V DVCC Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . VEE to VCC Analog Input Current . . . . . . . . . . . . . . 10 mA to +10 mA Digital Input Voltage (ENCODE) . . . . . . . . . . . . . 0 to VCC ENCODE, ENCODE Differential Voltage . . . . . . . . . . 4 V Digital Output Current . . . . . . . . . . . . 10 mA to +10 mA ENVIRONMENTAL2 Operating Temperature (Case) . . . . . . . . . 40°C to +85°C Maximum Junction Temperature . . . . . . . . . . . . . . . 175°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . 300°C Storage Temperature Range (Ambient) . . 65°C to +150°C
NOTES 1 Absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedance for "ES" package: JC, 2.2°C/W; JA, 24.3°C/W.
I II
100% Production Tested. 100% Production Tested at 25°C, and sample tested at specified temperatures. AC testing done on sample basis.
III Sample Tested Only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at temperature at 25°C: sample tested at temperature extremes.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD13465 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model AD13465AZ AD13465AF 5962-0150601HXA AD13465/PCB
Temperature Range (Case) 25°C to +85°C 25°C to +85°C 40°C to +85°C 25 °C
Package Description 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar 68-Lead Ceramic Leaded Chip Carrier Evaluation Board with AD13465AZ
Package Option ES-68C ES-68C ES-68C
4
REV. 0
AD13465
PIN FUNCTION DESCRIPTIONS
Pin No. 1, 35 2, 3, 9, 10, 13, 16 4 5 6 7 8 11 12 14 15 17 1825, 2833 26, 27 34 36 3742, 4552 43, 44 53 54, 57, 60, 61, 67, 68 55 56 58 59 62 63 64 65 66
Mnemonic SHIELD AGNDA AIN A+IN AMP-OUT-A AMP-IN-A-1 AMP-IN-A-2 A VE E A A VC C A ENCA ENCA DVCCA D0AD13A DGNDA DROUTA DROUTB D0BD13B DGNDB DVCCB AGNDB ENCB ENCB A VC C B A VE E B AMP-IN-B-2 AMP-IN-B-1 AMP-OUT-B B+IN BIN
Function Internal Ground Shield Between Channels. A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Inverting Differential Input (Gain = 1). Noninverting Differential Input (Gain = 1). Single-Ended Amplifier Output (Gain = 2). Analog Input for A Side ADC (Nominally ± 0.5 V). Analog Input for A Side ADC (Nominally ± 1.0 V). A Channel Analog Negative Supply Voltage (Nominally 5.0 V or 5.2 V). A Channel Analog Positive Supply Voltage (Nominally 5.0 V). Complement of Encode; Differential Input. Encode Input; Conversion Initiated on Rising Edge. A Channel Digital Positive Supply Voltage (Nominally 5.0 V/3.3 V). Digital Outputs for ADC A. D0 (LSB). A Channel Digital Ground. Data Ready A Output. Data Ready B Output. Digital Outputs for ADC B. D0 (LSB). B Channel Digital Ground. B Channel Digital Positive Supply Voltage (Nominally 5.0 V/3.3 V). B Channel Analog Ground. Encode Input; Conversion Initiated on Rising Edge. Complement of Encode; Differential Input. B Channel Analog Positive Supply Voltage (Nominally 5.0 V). B Channel Analog Negative Supply Voltage (Nominally 5.0 V or 5.2 V). Analog Input for B Side ADC (Nominally ± 1.0 V). Analog Input for B Side ADC (Nominally ± 0.5 V). Single-Ended Amplifier Output (Gain = 2). Noninverting Differential Input (Gain = 1). Inverting Differential Input (Gain = 1).
PIN CONFIGURATION
AMP-OUT-A A+IN B+IN AMP-OUT-B AMP-IN-A-2 AMP-IN-A-1 AMP-IN-B-1 AMP-IN-B-2 SHIELD AGNDB AGNDA AIN AGNDA AGNDA AGNDB AGNDB
60 AGNDB 59 AVEEB 58 AVCCB 57 AGNDB 56 ENCB 55 ENCB 54 AGNDB 53 DVCCB 52 D13B(MSB) 51 D12B 50 D11B 49 D10B 48 D9B 47 D8B 46 D7B 45 D6B 44 DGNDB 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 PIN 1 IDENTIFIER
AGNDA 10 AVEEA 11 AVCCA 12 AGNDA 13 ENCA 14 ENCA 15 AGNDA 16 DVCCA 17 D0A(LSB) 18 D1A 19 D2A 20 D3A 21 D4A 22 D5A 23 D6A 24 D7A 25 DGNDA 26
AD13465
TOP VIEW (Not to Scale)
D1B
BIN
D2B
D12A D13A(MSB)
REV. 0
5
DROUTB D0B(LSB)
DROUTA
DGNDA
SHIELD
DGNDB
D3B D4B
D8A
D9A D10A D11A
D5B
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