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Details, datasheet, quote on part number:AD10226
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Datasheet text preview:
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FEATURES Two Independent 12-Bit, 125 MSPS ADCs Channel-to-Channel Isolation, > 80 dB AC-Coupled Signal Conditioning Included Gain Flatness up to Nyquist, < 0.1 dB Input VSWR 1.1:1 to Nyquist 80 dB Spurious-Free Dynamic Range Two's Complement Output Format 3.3 V or 5 V CMOS-Compatible Output Levels 1.5 W Per Channel Single-Ended or Differential Input 3 50 MHz Input Bandwidth APPLICATIONS Wireless and Wired Broadband Communications Base Stations and "Zero-IF" or Direct IF Sampling Subsystems Wireless Local Loop (WLL) Local Multipoint Distribution Service (LMDS) Radar and Satellite Subsystems
Dual-Channel, 12-Bit 125 MSPS IF Sampling A/D Converter AD10226
PRODUCT DESCRIPTION
The AD10226 offers two complete ADC channels with on-module signal conditioning for improved dynamic performance. Each wide dynamic range ADC has a transformer coupled front end optimized for direct-IF sampling. The AD10226 has on-chip track-and-hold circuitry and utilizes an innovative architecture to achieve 12-bit, 125 MSPS performance. The AD10226 uses innovative high density circuit design to achieve exceptional performance, while still maintaining excellent isolation and providing for board area savings. The AD10226 operates with 5.0 V analog supply and 3.3 V digital supply. Each channel is completely independent, allowing operation with independent ENCODE and analog inputs. The AD10226 is available in a 35 mm square 385-lead BGA package.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 125 MSPS 2. Input signal conditioning included with full-power bandwidth to 350 MHz 3. Industry-leading IF sampling performance
FUNCTIONAL BLOCK DIAGRAM
AI N A 1 D0A (LSB) D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A D11A (MSB) DFS_A SFDR_A ENCODEA ENCODEA REF_A_OUT REF_B_OUT ENCODEB ENCODEB 12 12 12 12 ADC ADC T/H T/H T1A T1B
INA2
AI N B 1
INB2
D0B (LSB) D1B D2B D3B D4B
50 A
50 A
AD10226
D5B D6B D7B D8B D9B D10B D11B (MSB) DFS_B SFDR_B
OUTPUT RESISTORS TIMING REF REF
OUTPUT RESISTORS TIMING
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD10226SPECIFICATIONS
ELECTRICAL CHARACTERISTICS1 (V
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity2 Integral Nonlinearity2 No Missing Codes Gain Error3 Output Offset Gain Tempco Offset Tempco ANALOG INPUT Input Voltage Range Input Impedance Input VSWR4 Analog Input Bandwidth, High Analog Input Bandwidth, Low ANALOG REFERENCE Output Voltage Load Current Tempco SWITCHING PERFORMANCE5 Maximum Conversion Rate Minimum Conversion Rate Duty Cycle Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)6 Output Propagation Delay (tPD)6 Output Rise Time (tR) Output Fall Time (tF) DIGITAL INPUTS ENCODE Input Common-Mode Differential Input (ENC, ENC) Logic "1" Voltage Logic "0" Voltage Input Resistance Input Capacitance DIGITAL OUTPUTS Logic "1" Voltage6 Logic "0" Voltage6 Output Coding POWER SUPPLY7 Power Dissipation8 Power Supply Rejection Ratio Total I (DVDD) Current Total I (AVCC) Current Full Full Full 25 °C 25 °C Full Full 25 °C 25 °C Full Full Full 25 °C 25 °C Full Full Full Full 25 °C 25 °C Full Full 25 °C 25 °C Full Full Full Full Full 25 °C Full Full IV IV IV I I V V V V V IV IV V V V VI IV IV V V IV IV V V IV IV IV IV IV V IV IV 125 45 50 2.1 0.25 4.5 4.5 3.5 3.3 3.75 500 2.0 0.8 3 6 3 3.3 0 Two's Complement 3040 ± 0.5 40 540 10 55 0.99 1.3 9 12 Temp
DD =
3.3 V, VCC = 5.0 V; ENCODE = 125 MSPS, unless otherwise noted.)
Test Level Min Typ 12 ± 0.3 ± 0.75 Guaranteed ±1 +2 100 50 1.84 50 1.1:1 350 +0.99 +1.3 +9 +12 Max Unit Bits LSB LSB % FS LSB p p m /° C p p m /° C V p-p Ratio MHz MHz V mA p p m /° C MSPS MSPS % ns ps rms ns ns ns ns V mV V V k pF V V
1.25:1
300 1
2.5 5 ± 80
3.0
6.0
3.1
0.2
Full Full Full Full
VI IV VI VI
3300 ± 5.0 60 650
mW mV/V mA mA
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Parameter Temp Test Level Min Typ Max Unit DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR)9 (Without Harmonics) fIN = 10.3 MHz 25 °C fIN = 49 MHz 25 °C 25 °C fIN = 71 MHz fIN = 121 MHz 25 °C fIN = 250 MHz 25 °C Signal-to-Noise Ratio (SINAD)10 (With Harmonics) 25 °C fIN = 10.3 MHz fIN = 49 MHz 25 °C fIN = 71 MHz 25 °C 25 °C fIN = 121 MHz fIN = 250 MHz 25 °C Spurious-Free Dynamic Range11 fIN = 10 MHz 25 °C 25 °C fIN = 41 MHz fIN = 71 MHz 25 °C fIN = 121 MHz 25 °C 25 °C fIN = 250 MHz Two-Tone Intermodulation Distortion12 (IMD) fIN = 29.3 MHz; fIN = 30.3 MHz 25 °C 25 °C fIN = 150 MHz; fIN = 151 MHz Channel-to-Channel Isolation13 fIN = 121 MHz Full
I V I V V I V I V V I V I V V
66.5 63
68.5 67 66 64 60 68 66.5 65 62.5 59.5 82 77 72 71 70
dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
65.5 62.5
76.5 66
V V IV
78 70 85
dBc dBc dB
NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially, with the analog input applied to A INX1 and A INX2 tied to ground. 2 SFDR enabled (SFDR = 1) for DNL and INL specifications. 3 Gain error measured at 10.3 MHz. 4 Input VSWR, see TPC 14. 5 See Figure 1, Timing Diagram. 6 tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of ± 40 A. 7 Supply voltages should remain stable within ± 5% for normal operation. 8 Power dissipation measures with encode at rated speed. 9 Analog input signal power at 1 dBFS; signal-to-noise (SNR) is the ratio of signal level to total noise (first six harmonics removed). ENCODE = 125 MSPS, SFDR mode = 1. SNR is reported in dBFS, related back to converter full-scale. 10 Analog input signal power at 1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. ENCODE = 125 MSPS. SINAD is reported in dBFS, related back to converter full-scale. 11 Analog input signal equals 1 dBFS; SFDR is ratio of converter full-scale to worst spur. 12 Both input tones at 7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. 13 Channel-to-channel isolation tested with A channel/50 terminated (AIN A2) grounded and a full-scale signal applied to B channel (A IN B2). Specifications subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS
V DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . 5 V p-p (18 dBm) Digital Inputs . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature (Ambient) . . . . . . . 55°C to +125°C Storage Temperature (Ambient) . . . . . . . . . 65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Test Level I 100% production tested II 100% production tested at 25°C and sample tested at specific temperatures III Sample tested only IV Parameter is guaranteed by design and characterization testing V Parameter is a typical value only VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range
Table I. Output Coding (VREF = 2.5 V) (Two's Complement)
THERMAL CHARACTERISTICS
Code +2047 · · 0 1 · · 2048
AIN (V) +0.875 · · 0 0.000427 · · 0.875
Digital Output 0111 1111 1111 · · 0000 0000 0000 1111 1111 1111 · · 1000 0000 0000
385-Lead BGA Package: The typical JA of the module as determined by an IR scan is 2 6 . 2 5° C / W .
SAMPLE N 1 AIN
SAMPLE N
SAMPLE N 10
SAMPLE N 11
SAMPLE N 1
SAMPLE N 9
ENCODE ENCODE
1/f S
t PD tV
D11 D0 DATA N 11 DATA N 10 N9 N2 DATA N 1 DATA N DATA N 1
Figure 1. Timing Diagram
ORDERING GUIDE
Model AD10226AB AD10226/PCB
Temperature Range 25°C to +85°C (Ambient) 25 °C
Package Description 385-Lead BGA (35 mm 35 mm) Evaluation Board with AD10226AB
Package Option B-385
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10226 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN CONFIGURATION
25 24 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
35mm SQUARE BOTTOM VIEW
PIN FUNCTION DESCRIPTIONS
Mnemonic AGNDA REF_A_OUT NC A IN A1 A IN A2 A VC C A DGNDA D11AD0A ENCODEA ENCODEA DVCCA DGNDB D11BD0B AGNDB DVCCB ENCODEB ENCODEB REF_B_OUT A IN B1 A IN B2 A VC C B DFS SFDR Mode
Function A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. A Channel Internal Voltage Reference No connection Analog Input for A side ADC ( input) Analog Input for A side ADC (+ input) Analog Positive Supply Voltage (nominally 5.0 V) A Channel Digital Ground Digital Outputs for ADC A. D0 (LSB) Complement of ENCODE Data conversion initiated on the rising edge of ENCODE input. Digital Positive Supply Voltage (nominally 3.3 V) B Channel Digital Ground Digital Outputs for ADC B. D0 (LSB) B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Digital Positive Supply Voltage (nominally 3.3 V) Complement of ENCODE Data conversion initiated on rising edge of ENCODE input. B Channel Internal Voltage Reference Analog Input for B side ADC ( input) Analog Input for B side ADC (+ input) Analog Positive Supply Voltage (nominally 5.0 V) Data format select. Low = Two's Complement, High = Binary. CMOS control pin that enables (SFDR MODE = 1) a proprietary circuit that may improve the spurious free dynamic range (SFDR) performance. It is useful in applications where the dynamic range of the system is limited by discrete spurious frequency content caused by nonlinearities in the ADC transfer function. SFDR Mode = 0 for normal operation. 5
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