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Details, datasheet, quote on part number:AD10242
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| Part: | AD10242 |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => 10-14 bit |
| Description: | Dual Channel, 12-Bit, 40 MSPS MCM A/D Converter With Dc-coupled Analog Input Signal Conditioning (AD9042 Core ADC) |
| Company: | Analog Devices |
| Datasheet: | Download AD10242 datasheet File size : 277 kB |
| Request For quote: | Find where to buy AD10242
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Datasheet text preview:
a
Dual, 12-Bit, 40 MSPS MCM A/D Converter with Analog Input Signal Conditioning AD10242
The AD10242 operates with ± 5.0 V for the analog signal conditioning with a separate 5.0 V supply for the analog-to-digital conversion. Each channel is completely independent, allowing operation with independent encode or analog inputs. The AD10242 also offers the user a choice of analog input signal ranges to minimize additional signal conditioning required for multiple functions within a single system. The heart of the AD10242 is the AD9042, which is designed specifically for applications requiring wide dynamic range. The AD10242 is manufactured by Analog Devices on our MIL-PRF-38534 MCM line and is completely qualified. Units are packaged in a custom cofired ceramic 68-lead gull wing package and specified for operation from 55°C to +125°C. Contact the factory for additional custom options including those which allow the user to ac couple the ADC directly, bypassing the front end amplifier section. Also see the AD9042 data sheet for additional details on ADC performance.
PRODUCT HIGHLIGHTS
FEATURES Two Matched ADCs with Input Signal Conditioning Selectable Bipolar Input Voltage Range ( 0.5 V, 1.0 V, 2.0 V) Full MIL-STD-883B Compliant 80 dB Spurious-Free Dynamic Range Trimmed Channel-Channel Matching APPLICATIONS Radar Processing Communications Receivers FLIR Processing Secure Communications Any I/Q Signal Processing Application
PRODUCT DESCRIPTION
The AD10242 is a complete dual signal chain solution including onboard amplifiers, references, ADCs, and output buffering providing unsurpassed total system performance. Each channel is laser trimmed for gain and offset matching and provides channelto-channel crosstalk performance better than 80 dB. The AD10242 utilizes two each of the AD9632, OP279, and AD9042 in a custom MCM to gain space, performance, and cost advantages over solutions previously available.
1. Guaranteed sample rate of 40 MSPS. 2. Dynamic performance specified over entire Nyquist band; spurious signals @ 80 dBc for 1 dBFS input signals. 3. Low power dissipation: <2 W off ± 5.0 V supplies. 4. User defined input amplitude. 5. Packaged in 68-lead ceramic leaded chip carrier.
FUNCTIONAL BLOCK DIAGRAM
AIN3 AIN2 AIN1 UNEG UCOM UPOS AIN3 AIN2 AIN1
UPOS OP279 UCOM UNEG (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A ENC ENC D9A D10A D11A (MSB) D0B (LSB) D1B D2B D3B D4B D5B D6B TIMING 9 OUTPUT BUFFERING OUTPUT BUFFERING 7 12 OP279 VREF AD9042 OP279 AD9042 TIMING VREF ENC ENC OP279 AD9632 AD9632
AD10242
D11B (MSB) 12 5 D10B D9B D8B D7B
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD10242SPECIFICATIONS
Electrical Characteristics
Parameter RESOLUTION DC ACCURACY No Missing Codes Offset Error Offset Error Channel Match Gain Error1 Gain Error Channel Match ANALOG INPUT (AIN) Input Voltage Range AIN1 AIN2 AIN3 Input Resistance AIN1 AIN2 AIN3 Input Capacitance2 Analog Input Bandwidth3 ENCODE INPUT4, 5 Logic Compatibility Logic "1" Voltage Logic "0" Voltage Logic "1" Current (VINH = 5 V) Logic "0" Current (VINL = 0 V) Input Capacitance SWITCHING PERFORMANCE Maximum Conversion Rate6 Minimum Conversion Rate 6 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulsewidth High ENCODE Pulsewidth Low Output Delay (tOD) SNR7 Analog Input @ 1.2 MHz @ 4.85 MHz @ 9.9 MHz @ 19.5 MHz SINAD8 Analog Input @ 1.2 MHz @ 4.85 MHz @ 9.9 MHz @ 19.5 MHz Full 25° C Full Full 25° C Full Full VI I VI V I VI V 1, 2, 3 1 2, 3 1 2, 3
(AVCC = 5 V; AVEE = 5.0 V; DVCC = 5 V; applies to each ADC unless otherwise noted.)
Temp Test Level Mil Subgroup Min AD10242BZ/TZ Typ 12 G uaranteed ± 0.05 ± 1.0 ± 0.1 ± 0.5 ± 0.8 ± 0.1 Max Unit Bits
0.5 2.0 1.0 1.5
+0.5 +2.0 +1.0 +1.5
% FS % FS % % FS % FS %
Full Full Full Full Full Full 25° C Full
I I I IV IV IV IV V 12 12 12 12 99 198 396 0
± 0.5 ± 1.0 ±2 100 200 400 4.0 60 TTL/CMOS 101 202 404 7.0
V V V pF MHz
Full Full Full Full 2 5° C Full Full 25° C 25° C 2 5° C 25° C 25° C Full 25° C 25° C Full 25° C Full 25° C Full 25° C 25° C Full 25° C Full 25° C Full
I I I I V VI V V V V IV IV IV V I II I II I II V I II I II I II
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 12 4, 5, 6 12
2.0 0 400 625 300
5.0 0.8 800 7.0
V V µA µA pF MSPS MSPS ns ns ps rms ns ns ns dB dB dB dB dB dB dB dB dB dB dB dB dB dB
40
50 5 1.0 ± 2.0 1 10 10 12 68 66 66 65 65 63 62 67 65 64 64 63 61 60
12 12 12
12 10
41 14
4 5, 6 4 5, 6 4 5, 6
63 62 63 62 60 59
4 5, 6 4 5, 6 4 5, 6
62 61 60 60 58 58
2
REV. B
AD10242
Parameter SPURIOUS-FREE DYNAMIC RANGE 9 Analog Input @ 1.2 MHz @ 4.85 MHz @ 9.9 MHz @ 19.5 MHz TWO-TONE IMD REJECTION 10 F1, F2 @ 7 dBFS CHANNEL-TO-CHANNEL ISOLATION TRANSIENT RESPONSE LINEARITY Differential Nonlinearity (Encode = 20 MHz) Integral Nonlinearity (Encode = 20 MHz) OVERVOLTAGE RECOVERY TIME 12 VIN = 2.0 × FS VIN = 4.0 × FS DIGITAL OUTPUTS Logic Compatibility Logic "1" Voltage13 Logic "0" Voltage14 Output Coding POWER SUPPLY AVCC Supply Voltage I (AVCC) Current AVEE Supply Voltage I (AVEE) Current DVCC Supply Voltage I (DVCC) Current ICC (Total) Supply Current Power Dissipation (Total)
11
Temp 25° C 25° C Full 25° C Full 25° C Full Full 25° C 2 5° C 25° C Full 25° C
Test Level I I II I II I II II IV V IV IV V
Mil Subgroup
Min
AD10242BZ/TZ Typ Max 81 80 79 70 69 67 66 76 80 10
Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dB ns
4 5, 6 4 5, 6 4 5, 6 4, 5, 6 12
70 70 63 63 60 60 70 75
12 12
0.3 0.5 0.3
1.0 1.25
LSB LSB
Full
Full
V
IV 12
0.5
50 100
LSB LSB
ns
Full
IV
12
75
200
ns
Full Full
I I
1, 2, 3 1, 2, 3
3.5
CMOS 4.2 0.45 0.65 Two's Complement 5.0 260 5.0 55 5.0 25 350 1.75
V V
Full Full Full Full Full Full Full Full
VI V VI V VI V I I
1, 2, 3 1, 2, 3
400 2.0
V mA V mA V mA mA W
Power Supply Rejection Ratio (PSRR) Pass Band Ripple to 10 MHz
Full Full
I IV
7, 8 12
0.01
0.02 0.2
% FSR/% VS dB
NOTES 1 Gain tests are performed on A IN3 over specified input voltage range. 2 Input capacitance specifications combine AD9632 die capacitance and ceramic package capacitance. 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor. 5 ENCODE may also be driven differentially in conjunction with ENCODE; see Encoding the AD10242 section for details. 6 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 7 Analog Input signal power at 1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 40.0 MSPS. 8 Analog Input signal power at 1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 40.0 MSPS. 9 Analog Input signal equal 1 dBFS; SFDR is ratio of converter full scale to worst spur. 10 Both input tones at 7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 10.0 MHz ± 100 kHz, 50 kHz f1 f2 300 kHz. 11 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (A IN1). 12 Input driven to 2× and 4× AIN1 range for >4 clock cycles. Output recovers inband in specified time with Encode = 40 MSPS. No foldover guaranteed. 13 Outputs are sourcing 10 µA. 14 Outputs are sinking 10 µA. All specifications guaranteed within 100 ms of initial power-up regardless of sequencing. Specifications subject to change without notice.
REV. B
3
AD10242
ABSOLUTE MAXIMUM RATINGS 1 Parameter ELECTRICAL VCC Voltage VEE Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current ENVIRONMENTAL 2 Operating Temperature (Case) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Min 0 7 V EE 10 0 40 55 Max 7 0 V CC +10 V CC 4 +40 +125 175 300 +150 Unit V V V mA V V mA °C °C °C °C Table I. Output Coding
MSB
LSB
Base 10 2047 +1 0 1 2048
Input +FS 0.0 V FS
0111111111111 0000000000001 0000000000000 1111111111111 1000000000000
EXPLANATION OF TEST LEVELS
65
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances for "Z" package: JC = 11°C/W; JA = 30°C/W.
Test Level I 100% Production Tested. II 100% production tested at 25°C, and sample tested at specified temperatures. AC testing done on sample basis. III Sample Tested Only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI All devices are 100% production tested at 25°C; sample tested at temperature extremes.
ORDERING GUIDE
Model
Temperature Range 40°C to +85°C (Case) 55°C to +125°C (Case) 55°C to +125°C (Case) 55°C to +125°C (Case) 2 5 °C
Package Description 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier Evaluation Board with AD10242BZ
Package Option Z-68A Z-68A Z-68A Z-68A
AD10242BZ AD10242TZ AD10242TZ/883B 5962-9581501HXA AD10242/PCB
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10242 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4
REV. B
AD10242
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2, 5, 911, 2627 3 4 6 7 8 12 13 14 1516 1725, 3133 28 29 30 3435 3642, 4549 4344, 5354 5861, 65, 68 50 51 52 55 56 57 62 63 64 66 67
Mnemonic SHIELD GNDA UNEGA UCOMA A I NA 1 A I NA 2 A I NA 3 UPOSA AV EE AV CC NC D0AD11A ENCODEA ENCODEA DV CC NC D0BD11B GNDB DV CC ENCODEB ENCODEB UCOMB UNEGB UPOSB A INB 1 A INB 2 A INB 3 AV CC AV EE
Function Internal Ground Shield between Channels. A Channel Ground. A and B grounds should be connected as close to the device as possible. Unipolar Negative. Unipolar Common. Analog Input for A Side ADC (Nominally ± 0.5 V). Analog Input for A Side ADC (Nominally ± 1.0 V). Analog Input for A Side ADC (Nominally ± 2.0 V). Unipolar Positive. Analog Negative Supply Voltage (Nominally 5.0 V or 5.2 V). Analog Positive Supply Voltage (Nominally +5.0 V). No Connect. Digital Outputs for ADC A. D0 (LSB). ENCODE is complement of ENCODE. Data conversion initiated on rising edge of ENCODE input. Digital Positive Supply Voltage (Nominally +5.0 V). No Connect. Digital Outputs for ADC B. D0 (LSB). B Channel Ground. A and B grounds should be connected as close to the device as possible. Digital Positive Supply Voltage (Nominally +5.0 V). Data conversion initiated on rising edge of ENCODE input. ENCODE is complement of ENCODE. Unipolar Common. Unipolar Negative. Unipolar Positive. Analog Input for B Side ADC (Nominally ± 0.5 V). Analog Input for B Side ADC (Nominally ± 1.0 V). Analog Input for B Side ADC (Nominally ± 2.0 V). Analog Positive Supply Voltage (Nominally +5.0 V). Analog Negative Supply Voltage (Nominally 5.0 V or 5.2 V).
PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier
GNDA UCOMA UNEGA GNDA SHIELD GNDB AVEE GNDA AINA3 GNDB AINB3 AVCC GNDB AINA2 AINA1 AINB2 AINB1
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 PIN 1 IDENTIFIER 60 59 58
GNDA
10
GNDB
GNDA 11 UPOSA 12 AVEE 13 AVCC 14 NC 15 NC 16 (LSB) D0A 17 D1A 18 D2A 19 D3A 20 D4A 21 D5A 22 D6A 23 D7A 24 D8A 25 GNDA 26
GNDB GNDB 57 UPOSB 56 UNEGB
55 54
UCOMB GNDB GNDB ENCODEB ENCODEB DVCC D11B (MSB) D10B D9B D8B D7B GNDB
AD10242
TOP VIEW (Not to Scale)
53 52 51 50 49 48 47 46 45 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
(MSB) D11A NC NC
ENCODEA ENCODEA DVCC D9A
D1B D2B
GNDA
D3B D4B
(LSB) D0B
NC = NO CONNECT
REV. B
5
D6B GNDB
D10A
D5B
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