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Details, datasheet, quote on part number:AD10265/PCB
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| Part: | AD10265/PCB |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => 10-14 bit |
| Description: | Dual Channel, 12-Bit, 65 MSPS A/D Converter With Ac-coupled Analog Input Signal Conditioning (AD6640 Core ADC) |
| Company: | Analog Devices |
| Datasheet: | Download AD10265/PCB datasheet File size : 2461 kB |
| Request For quote: | Find where to buy AD10265/PCB
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Datasheet text preview:
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Dual Channel, 12-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning AD10265
performance. The AD10265 uses innovative high-density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional matching and performance while still maintaining excellent isolation, and providing for significant board area savings. The AD10265 operates with ± 5.0 V for the analog signal conditioning with a separate +3.3 V supply for the analog-todigital conversion. Each channel is completely independent allowing operation with independent Encode and Analog inputs. The AD10265 also offers the user a choice of Analog Input Signal ranges to further minimize additional external signal conditioning, while still remaining general-purpose. The AD10265 is packaged in a 68-lead ceramic gull wing package, footprint compatible with the earlier generation AD10242 (12-bit, 40 MSPS). Manufacturing is done on Analog Devices' MIL-38534 Qualified Manufacturers Line (QML) and components are available up to Class-T (25°C to +125°C). The AD6640 internal components are manufactured on Analog Devices' high-speed complementary bipolar process (XFCB).
PRODUCT HIGHLIGHTS
FEATURES Dual, 65 MSPS Minimum Sample Rate Channel-Channel Matching, 0.1% Gain Error Channel-Channel Isolation, >80 dB AC-Coupled Signal Conditioning Included Selectable Bipolar Input Voltage Range ( 0.5 V, 1.0 V, 2.0 V) Gain Flatness up to Nyquist: < 0.5 dB 80 dB Spurious-Free Dynamic Range Two's Complement Output Format 3.3 V or 5 V CMOS-Compatible Output Levels 1.05 W Per Channel Industrial and Military Grade APPLICATIONS Phased Array Receivers Communications Receivers FLIR Processing Secure Communications GPS Anti-Jamming Receivers Multichannel, Multimode Receivers PRODUCT DESCRIPTION
The AD10265 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module includes two wide dynamic range AD6640 ADCs. Each AD6640 has an AD9631/AD9632 ac-coupled amplifier front end. The AD6640s have on-chip track-and-hold circuitry, and utilize an innovative multipass architecture, to achieve 12-bit, 65 MSPS
1. Guaranteed sample rate of 65 MSPS. 2. Input amplitude options, user configurable. 3. Input signal conditioning included; both channels matched for gain. 4. Fully tested/characterized performance for full channel. 5. Footprint compatible family; 68-lead LCCC.
FUNCTIONAL BLOCK DIAGRAM
AINA3 AINA2 AINA1 AINB3 AINB2 AINB1
AD9632 (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A 9 OUTPUT BUFFERING TIMING AD6640 12 AIN AIN
AD9631
AD9632
AD9631
AIN
AIN
TIMING
ENCODEB ENCODEB
AD10265
AD6640 D11B (MSB) 12 OUTPUT BUFFERING 7 5 D10B D9B D8B D7B
ENCODEA ENCODEA
D9A
D10A
D11A (MSB)
D0B (LSB)
D1B
D2B
D3B
D4B
D5B
D6B
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD10265SPECIFICATIONS
Electrical Characteristics (AV
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error1 Gain Error Channel Match Pass Band Ripple to Nyquist ANALOG INPUT (AIN) Input Voltage Range AIN1 AIN2 AIN3 Input Resistance AIN1 AIN2 AIN3 Input Capacitance2 Analog Input Bandwidth High 3 Analog Input Bandwidth Low 3 ENCODE INPUT4, 5 Logic Compatibility Logic "1" Voltage Logic "0" Voltage Logic "1" Current (VINH = 5 V) Logic "0" Current (VINL = 0 V) Input Capacitance SWITCHING PERFORMANCE Maximum Conversion Rate6 Minimum Conversion Rate 6 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulsewidth High ENCODE Pulsewidth Low Output Delay (tOD) SNR7 Analog Input @ 1.24 MHz @ 17 MHz @ 32 MHz SINAD8 Analog Input @ 1.24 MHz @ 17 MHz @ 32 MHz Full Full 25° C Full Full Full IV IV I VI V IV 12 2, 3 1 2, 3 12
CC
= +5 V; AVEE = 5.0 V; DVCC = +3.3 V; applies to each ADC unless otherwise noted.)
Test Level Mil Subgroup Min AD10265AZ Typ 12 Guaranteed +3.5 ± 0.5 ± 0.8 ± 0.2 0.2 Max Unit Bits
Temp
10 1.5 2.5
+10 +1.5 +2.5 0.5
mV % FS % FS % dB
Full Full Full Full Full Full 25° C 25° C 25° C
V V V IV IV IV IV V V IV IV IV IV IV IV VI IV V V V IV IV IV I II I II I II I II I II I II 12 12 12 12 99 198 396 0
± 0.5 ± 1.0 ±2 100 200 400 4.0 160 50 TTL/CMOS 2.0 0 500 400 12 4, 5, 6 12 65 6.5 400 ± 2.0 0.3 12 12 12 4 5, 6 4 5, 6 4 5, 6 4 5, 6 4 5, 6 4 5, 6 6.5 6.5 7.0 62 60.5 61 60 61 59.5 61 60 61 59.5 61 59 5.0 0.8 800 200 7.0 101 202 404 7.0
V V V pF MHz kHz
Full Full Full Full 2 5° C Full Full 25° C 25° C 2 5° C 25° C 25° C Full 25° C Full 25° C Full 25° C Full 25° C Full 25° C Full 25° C Full
650 320 4.5
V V µA µA pF MSPS MSPS ps ns ps rms ns ns ns dB dB dB dB dB dB dB dB dB dB dB dB
9.0 66 66 65 65 63 62 65 64 64 63 62 62
12.5
2
REV. A
AD10265
Parameter SPURIOUS-FREE DYNAMIC RANGE Analog Input @ 1.24 MHz @ 17 MHz @ 32 MHz TWO-TONE IMD REJECTION 10 f1, f2 @ 7 dBFS CHANNEL-TO-CHANNEL ISOLATION LINEARITY Differential Nonlinearity (Encode = 20 MHz) Integral Nonlinearity (Encode = 20 MHz) DIGITAL OUTPUTS Logic Compatibility Logic "1" Voltage Logic "0" Voltage Output Coding POWER SUPPLY AVCC Supply Voltage I (AVCC) Current AVEE Supply Voltage I (AVEE) Current DVCC Supply Voltage I (DVCC) Current ICC (Total) Supply Current Power Dissipation (Total) Power Supply Rejection Ratio (PSRR)
11 9
Temp 25° C Full 25° C Full 25° C Full Full 25° C
Test Level I II I II V V V IV
Mil Subgroup 4 5, 6 4 5, 6
Min 75 74 71 70
AD10265AZ Typ 80 80 80 79 79 79 77
Max
Unit dBFS dBFS dBFS dBFS dBFS dBFS dBc dB
4, 5, 6 12
66 80
2 5° C Full
IV V
12
1.0
± 0.5 ± 1.25
+1.5
LSB LSB
Full Full
I I
1, 2, 3 1, 2, 3
2.8
CMOS DVCC 0.2 0.2 0.5 Two's Complement +5.0 336 5.0 66 +3.3 20 422 2.1 0.01
V V
Full Full Full Full Full Full Full Full Full
V V V V V V I I IV
1, 2, 3 1, 2, 3 12
520 2.4 0.02
V mA V mA V mA mA W % FSR/% VS
NOTES 1 Gain tests are performed on A IN1 over specified input voltage range. 2 Input capacitance specifications show only ceramic package capacitance. 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor. 5 ENCODE may also be driven differentially in conjunction with ENCODE; see "Encoding the AD10265" for details. 6 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 7 Analog Input signal power at 1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 65 MSPS. 8 Analog Input signal power at 1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. 9 Analog Input signal equal 1 dBFS; SFDR is ratio of converter full scale to worst spur. 10 Both input tones at 7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 17.0 MHz ± 100 kHz, f2 = 18.0 MHz ± 100 kHz. 11 Channel-to-channel isolation tested with A channel/50 ohm terminated
REV. A
3
AD10265
ABSOLUTE MAXIMUM RATINGS 1 Parameter ELECTRICAL VCC Voltage VEE Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current ENVIRONMENTAL Operating Temperature (Case) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient)
2
Table I. Output Coding Min 0 7 V EE 10 0 10 55 Max +7 0 V CC +10 A V CC 4 +10 +125 175 300 +150 Unit V V V mA V V mA °C °C °C °C
MSB
LSB
Base 10 2047 +1 0 1 2048
Input +FS 0.0 V FS
0111111111111 0000000000001 0000000000000 1111111111111 1000000000000
EXPLANATION OF TEST LEVELS
65
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances for "Z" package: JC = 11°C/W; JA = 30°C/W.
Test Level I. 100% production tested. II. 100% production tested at 25°C, and sample tested at specified temperatures. AC testing done on sample basis. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. All devices are 100% production tested at 25°C; sample tested at temperature extremes.
ORDERING GUIDE
Model
Temperature Range 25°C to +85°C (Case) + 2 5° C 25°C to +125°C (Case) 25°C to +125°C (Case)
Package Description 68-Lead Ceramic Leaded Chip Carrier Evaluation Board with AD10265AZ 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier
Package Option ES-68C ES-68C ES-68C
AD10265AZ AD10265/PCB 5962-9865901 HXA 5962R0151901 TXA
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10265 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4
REV. A
AD10265
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2, 5, 911, 26, 27 3, 4, 12, 15, 16, 34, 35, 5557 6 7 8 13 14 1725, 3133 28 29 30 3642, 4549 43, 44, 53, 54, 5861, 65, 68 50 51 52 62 63 64 66 67
Name SHIELD GNDA NC A I NA 1 A I NA 2 A I NA 3 AV EE AV CC D0AD11A ENCODEA ENCODEA DV CC D0BD11B GNDB DV CC ENCODEB ENCODEB A INB 1 A INB 2 A INB 3 AV CC AV EE
Function Internal Ground Shield between channels. A Channel Ground. A and B grounds should be connected as close to the device as possible. No Connect. Pins 15 and 16 are internal test pins: it is recommended to connect them to GND. Analog Input for A side ADC (nominally ± 0.5 V). Analog Input for A side ADC (nominally ± 1.0 V). Analog Input for A side ADC (nominally ± 2.0 V). Analog Negative Supply Voltage (nominally 5.0 V). For A side ADC. Analog Positive Supply Voltage (nominally +5.0 V). For A side ADC. Digital Outputs for ADC A. D0 (LSB). ENCODE is complement of ENCODE. Data conversion initiated on rising edge of ENCODE input. Digital positive supply voltage (nominally 3.3 V) for A side ADC. Digital Outputs for ADC B. D0 (LSB). B Channel Ground. A and B grounds should be connected as close to the device as possible. Digital Positive Supply Voltage (nominally 3.3 V) for B side ADC. Data conversion initiated on rising edge of ENCODE input. ENCODE is complement of ENCODE. Analog Input for B side ADC (nominally ± 0.5 V). Analog Input for B side ADC (nominally ± 1.0 V). Analog Input for B side ADC (nominally ± 2.0 V). Analog Positive Supply Voltage (nominally +5.0 V). For B side ADC. Analog Negative Supply Voltage (nominally 5.0 V). For B side ADC.
PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier
GNDA AINA3 AINA2 AINA1 GNDA NC NC GNDA SHIELD GNDB AVEE AVCC GNDB AINB3 AINB2 AINB1
9 8 7 6 5 4 3 2
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
GNDA GNDA NC AVEE AVCC NC NC (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A GNDA
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
GNDB
PIN 1
AD10265
TOP VIEW (Not to Scale)
GNDB GNDB GNDB NC NC NC GNDB GNDB ENCODEB ENCODEB DVCC D11B (MSB) D10B D9B D8B D7B GNDB
NC = NO CONNECT
REV. A
GNDA ENCODEA ENCODEA DVCC D9A D10A (MSB) D11A NC NC (LSB) D0B D1B D2B D3B D4B D5B D6B GNDB
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