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Details, datasheet, quote on part number:AD10465AZ
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Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning AD10465
utilize an innovative multipass architecture to achieve 14-bit, 65 MSPS performance. The AD10465 uses innovative highdensity circuit design and laser-trimmed thin-film resistor networks to achieve exceptional matching and performance, while still maintaining excellent isolation and providing for significant board area savings. The AD10465 operates with ±5.0 V for the analog signal conditioning with a separate 5.0 V supply for the analog-to-digital conversion and 3.3 V digital supply for the output stage. Each c h a n n e l is completely independent, allowing operation with i n d e p e n d e n t encode and analog inputs. The AD10465 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while still remaining general-purpose. The AD10465 is packaged in a 68-lead Ceramic Gull Wing package, footprint-compatible with the earlier generation AD10242 (12-bit, 40 MSPS) and AD10265 (12-bit, 65 MSPS). Manufactu r i n g is done on Analog Devices, Inc. Mil-38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (40°C to +85°C). The AD6644 internal components are manufactured on Analog Devices, Inc. high-speed complementary bipolar process (XFCB).
PRODUCT HIGHLIGHTS
FEATURES Dual, 65 MSPS Minimum Sample Rate Channel-to-Channel Matching, 0.5% Gain Error Channel-to-Channel Isolation, >90 dB DC-Coupled Signal Conditioning Included Selectable Bipolar Input Voltage Range ( 0.5 V, 1.0 V, 2.0 V) Gain Flatness up to 25 MHz: < 0.2 dB 80 dB Spurious-Free Dynamic Range Two's Complement Output Format 3.3 V or 5 V CMOS-Compatible Output Levels 1.75 W per Channel Industrial and Military Grade APPLICATIONS Phased Array Receivers Communications Receivers FLIR Processing Secure Communications GPS Antijamming Receivers Multichannel, Multimode Receivers PRODUCT DESCRIPTION
The AD10465 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module includes two wide dynamic range AD6644 ADCs. Each AD6644 has a dccoupled amplifier front end including an AD8037 low distortion, high bandwidth amplifier, providing a high input impedance and gain, and driving the AD8138 single-to-differential amplifier. The AD6644s have on-chip track-and-hold circuitry and
1. Guaranteed sample rate of 65 MSPS. 2. Input amplitude options, user configurable. 3. Input signal conditioning included; both channels matched for gain. 4. Fully tested/characterized performance. 5. Footprint compatible family; 68-lead LCC.
FUNCTIONAL BLOCK DIAGRAM
AINA3 AINA2 AINA1 REF A AINB3 AINB2 AINB1
DRAOUT D0A (LSB) D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A TIMING ENC ENC 11 VREF DROUT 14 OUTPUT BUFFERING 3 VREF DROUT 14 OUTPUT BUFFERING 9 5 REF B DRBOUT
AD10465
ENC TIMING ENC D13B D12B D11B D10B D9B
D11A D12A D13A (MSB)
D0B (LSB) D1B D2B D3B D4B D5B
D6B D7B D8B
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD10465SPECIFICATIONS (AV
Parameter RESOLUTION DC ACCURACY No Missing Codes Offset Error Offset Error Channel Match Gain Error1 Gain Error Channel Match
CC
= +5 V; AVEE = 5 V; DVCC = 3.3 V applies to each ADC unless otherwise noted.)
Test Level Mil Subgroup AD10465AZ/BZ/QML-H Min Typ Max 14 Unit Bits
Temp
Full 25° C Full Full 25° C Full 25° C Max Min
VI I VI V I VI I I I
1, 2, 3 1 2, 3 1 2, 3 1 2 3
2.2 2.2 1 3 5 1.5 3 5
Guaranteed ± 0.02 ± 1.0 ± 1.0 1.0 ± 2.0 ± 0.5 ± 1.0
+2.2 +2.2 +1 +1 +5 +1.5 +3 +5
% FS % FS % % FS % FS % % %
ANALOG INPUT (AIN) Input Voltage Range AIN1 AIN2 AIN3 Input Resistance AIN1 AIN2 AIN3 Input Capacitance2 Analog Input Bandwidth3 ENCODE INPUT (ENC, ENC)4 Differential Input Voltage 17 Differential Input Resistance Differential Input Capacitance SWITCHING PERFORMANCE Maximum Conversion Rate 5 Minimum Conversion Rate 5 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulsewidth High ENCODE Pulsewidth Low Output Delay (tOD) Encode, Rising to Data Ready, Rising Delay (T E_DR) SNR6 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 19.5 MHz Analog Input @ 32.1 MHz SINAD7 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 19.5 MHz Analog Input @ 32.1 MHz
Full Full Full Full Full Full 25° C Full Full 2 5° C 2 5° C Full Full 25° C 25° C 2 5° C 25° C 25° C Full Full 25° C 25° C Full 25° C Full 25° C Full 25° C 25° C Full 25° C Full 25° C Full
V V V IV IV IV IV V IV V V VI V V IV V IV IV V 4, 5, 6 12 12 12 12 6.2 6.2 12 12 12 12 99 198 396 0
± 0.5 ± 1.0 ±2 100 200 400 4.0 100 101 202 404 7.0
V V V pF MHz V p-p k pF MSPS MSPS ns ps ps rms ns ns ns ns dBFS dBFS dBFS dBFS dBFS dBFS dBFS dB dB dB dB dB dB dB
0.4 10 2.5 65 20 1.5 250 0.3 7.7 7.7 6.8 11.5 70 70 70 70 70 69 69 70 69 69 68 68 63 61 500 9.2 9.2
V I II I II I II V I II I II I II
4 5, 6 4 5, 6 4 5, 6
69 68 68 67 67 67
4 5, 6 4 5, 6 4 5, 6
67.5 67.5 65 65 60 58
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Parameter SPURIOUS-FREE DYNAMIC RANGE Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 19.5 MHz Analog Input @ 32.1 MHz TWO-TONE IMD REJECTION 9 fIN = 10 MHz and 11 MHz f1 and f2 are 7 dB fIN = 31 MHz and 32 MHz f1 and f2 Are 7 dB CHANNEL-TO-CHANNEL ISOLATION 10 TRANSIENT RESPONSE OVERVOLTAGE RECOVERY TIME VIN = 2.0 × fS VIN = 4.0 × fS DIGITAL OUTPUTS 12 Logic Compatibility DVCC = 3.3 V Logic "1" Voltage Logic "0" Voltage D V CC = 5 V Logic "1" Voltage Logic "0" Voltage Output Coding POWER SUPPLY AVCC Supply Voltage13 I (AVCC) Current AVEE Supply Voltage13 I (AVEE) Current DVCC Supply Voltage13 I (DVCC) Current ICC (Total) Supply Current per Channel Power Dissipation (Total) Power Supply Rejection Ratio (PSRR) Passband Ripple to 10 MHz Passband Ripple to 25 MHz
11 8
Temp 2 5 °C 2 5 °C Full 2 5 °C Full 2 5 °C Full 2 5 °C 2 5 °C Full 2 5 °C 2 5 °C Full Full
Test Level V I II I II I II I II I II IV V IV IV
Mil Subgroup
AD10465AZ/BZ/QML-H Min Typ Max 85 82 82 78 78 68 66 87 70 90 15.3
Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dB ns
4 5, 6 4 5, 6 4 5, 6 4 5, 6 4 5, 6 12
73 70 72 70 62 60 78 78 68 60
12 12
40 150 CMOS
100 200
ns ns
Full Full Full Full
I I V V
1, 2, 3 1, 2, 3
2.5
DVCC 0.2 0.2
0.5
V V V V
DVCC 0.3 0.35 Two's Complement 4.85 5.25 3.135 1, 2, 3 1, 2, 3 5.0 270 5.0 38 3.3 30 338 3.5 0.02 0.1 0.2 5.25 308 4.75 49 3.465 46 403 3.9
Full Full Full Full Full Full Full Full Full
VI I VI V VI V I I V V V
V mA V mA V mA mA W % FSR/% VS dB dB
NOTES 1 Gain tests are performed on A IN1 input voltage range. 2 Input Capacitance spec. combines AD8037 die capacitance and ceramic package capacitance. 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 All ac specifications tested by driving ENCODE and ENCODE differentially. 5 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 6 Analog input signal power at 1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR is reported in dBFS, related back to converter full power. 7 Analog input signal power at 1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. 8 Analog input signal power swept from 1 dBFS to 60 dBFS; SFDR is ratio of converter full scale to worst spur. 9 Both input tones at 7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. 10 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel. 11 Input driven to 2× and 4× AIN1 range for > four clock cycles. Output recovers inband in specified time with Encode = 65 MSPS. 12 Digital output logic levels: DV CC = 3.3 V, CLOAD = 10 pF. Capacitive loads > 10 pF will degrade performance. 13 Supply voltage recommended operating range. AV CC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. All specifications guaranteed within 100 ms of initial power-up regardless of sequencing. Specifications subject to change without notice.
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AD10465
ABSOLUTE MAXIMUM RATINGS 1 Parameter ELECTRICAL VCC Voltage VEE Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current ENVIRONMENTAL 2 Operating Temperature (Case) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Min Max Units 0 7 V EE 10 0 10 40 7 0 V CC +10 V CC 4 +10 +85 174 300 +150 V V V mA V V mA °C °C °C °C TEST LEVEL
I. 100% Production Tested. II. 100% Production Tested at 25°C, and sample tested at specified temperatures. AC testing done on sample basis. III. Sample Tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at temperature at 25°C, sample tested at temperature extremes.
65
NOTES 1 Absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedance for "ES" package: JC = 2.2°C/W; JA = 24.3°C/W.
ORDERING GUIDE
Model AD10465AZ AD10465BZ 5962-9961601HXA AD10465/PCB
Temperature Range 25°C to +85°C (Case) 40°C to +85°C (Case) 40°C to +85°C (Case) 25 °C
Package Description 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier Evaluation Board with AD10465AZ
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10465 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN FUNCTION DESCRIPTIONS
Pin No. 1 2, 4, 5, 911 3 6 7 8 12 13 14 26, 27 1525, 3133 28 29 30 43, 44 3442, 4549 5354, 5761, 65, 68 50 51 52 55 56 62 63 64 66 67
Name SHIELD AGNDA REF_A AINA1 AINA2 AINA3 DRAOUT A VE E A VC C DGNDA D0AD13A ENCODEA ENCODEA DVCC DGNDB D0B-D13B AGNDB DVCC ENCODEB ENCODEB DRBOUT REF_B AINB1 AINB2 AINB3 A VC C A VE E
Function Internal Ground Shield between channels. A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. A Channel Internal Voltage Reference. Analog Input for A side ADC (nominally ± 0.5 V). Analog Input for A side ADC (nominally ± 1.0 V). Analog Input for A side ADC (nominally ± 2.0 V). Data Ready A Output. Analog Negative Supply Voltage (nominally 5.0 V or 5.2 V). Analog Positive Supply Voltage (nominally 5.0 V). A Channel Digital Ground. Digital Outputs for ADC A. D0 (LSB). ENCODE is complement of ENCODE. Data conversion initiated on rising edge of ENCODE input. Digital Positive Supply Voltage (nominally 5.0 V/3.3 V). B Channel Digital Ground. Digital Outputs for ADC B. D0 (LSB). B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Digital Positive Supply Voltage (nominally 5.0 V/3.3 V). Data conversion initiated on rising edge of ENCODE input. ENCODE is complement of ENCODE. Data Ready B Output. B Channel Internal Voltage Reference. Analog Input for B side ADC (nominally ± 0.5 V). Analog Input for B side ADC (nominally ± 1.0 V). Analog Input for B side ADC (nominally ± 2.0 V). Analog Positive Supply Voltage (nominally 5.0 V). Analog Negative Supply Voltage (nominally 5.0 V or 5.2 V). .
PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier
SHIELD AGNDB AVCC AGNDB A I N B3 AGNDA AGNDA REF A AGNDA AGNDA AVEE AGNDB
60 AGNDB 59 AGNDB 58 AGNDB 57 AGNDB 56 REF B 55 DRBOUT 54 AGNDB 53 AGNDB 52 ENCODEB 51 ENCODEB 50 DVCC 49 D13B(MSBB) 48 D12B 47 D11B 46 D10B 45 D9B 44 DGNDB 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
9
8
AINA1 AINA2 AINA3
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 PIN 1 IDENTIFIER
AGNDA 10 AGNDA 11 DRAOUT 12 AVEE 13 AVCC 14 D0A(LSBA) 15 D1A 16 D2A 17 D3A 18 D4A 19 D5A 20 D6A 21 D7A 22 D8A 23 D9A 24 D10A 25 DGNDA 26
AD10465
TOP VIEW (Not to Scale)
D1B
D2B
D4B
D5B
D6B
D3B
D7B
D8B
A I N B2 A I N B1
ENCODEA ENCODEA
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D12A D13A(MSBA)
D0B(LSBB)
DGNDA
5
DGNDB
DVCC D11A
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