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Details, datasheet, quote on part number:AD1803
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Datasheet text preview:
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FEATURES Low Power Modem Telephony Codec 16-Bit Oversampling - Converter Technology Intel AC'97 Rev 2.1-Compliant Modem Codec Implementation AC'97 or DSP Style Serial Interface Supports All Modem/Fax Standards Including V.90 Multiple Crystal/Clock Rates Supported Programmable Gain, Attenuation and Mute On-Chip Signal Filters Digital Interpolation and Decimation Filters Analog Output Low Pass Programmable Sample Rates From 6.4 kHz to 16 kHz With 1 Hz, 8/7 Hz and 10/7 Hz Resolution
Modem/ Telephony Codec AD1803
Digital Codec Engine with Variable Sample Rate Conversion Digital Monitor Speaker Output 24-Lead TSSOP Package 0.6 m CMOS Technology Operation from 3.3 V or 5 V Supply Advanced Power Management APPLICATIONS Modems (PC and Embedded) Voice and Telephony Fax Machines, Answering Machines, Speakerphones PBX Systems Smart Appliances REFERENCE DESIGN Available
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DVDD DGND BIT_CLK SYNC SDATA_IN SDATA_OUT RESET ADC FILTER +20dB - ADC MUX
AD1803
VOLTAGE REFERENCE
VREF
G[1]/MIC Rx FILT
AC'97/DSP SERIAL PORT
PWM BLOCK
G[4]/MOUT
DAC FILTER
- MODULATOR
DAC FILTER + GAIN /ATTEN
Tx
ADDRESS REGISTER
GENERAL-PURPOSE I/O
CONTROL REGISTERS
G[0] G[2] G[3]/WAKE G[5] G[6] G[7]
REGISTER CONTROL LOGIC CLK_OUT XTALO
XTALI
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD1803SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature Digital Supply Analog Supply Sample Rate (fS) Input Signal Analog Output Pass Band ADC FFT Size DAC FFT Size VIH VIL VOH VOL IOH IOL
ADC RECEIVE PATH
25°C 3.3 V/5 V 3.3 V/5 V 8 kHz 1008 Hz 20 Hz to 4 kHz 512 4096 2.1 V 1.2 V 2.9 V 0.3 V 2.0 mA +2.0 mA
DAC Output Test Conditions 0 dB Attenuation Relative to Full-Scale Input 0 dB Mute Off 10 k Output Load ADC Input Test Conditions Autocalibrated 0 dB PGA Gain Mute Off Input 1.0 dB Relative to Full-Scale
Min Full-Scale Input Voltage (RMS Values Assume Sine Wave Input, PGA Gain = 0 dB, Offset Error = 0% of FS) AD1803 Rx Input (0 dBm) Resistance--Rx Input* with 0 dB Gain with +20 dB Gain Capacitance--Rx Input* Rx Programmable Gain Gain Step Size (0 dB to 42.5 dB, All Steps Tested) Input Gain Span (Note: The ADC Gain is achieved using a 0 dB to 22.5 dB Variable Gain Stage and a 20 dB Fixed Gain Stage. The 22.5 dB to 42.5 dB Gain Steps are achieved by enabling the 20 dB Gain Stage.) Analog-to-Digital Converter Dynamic Range (60 dB Input, THD+N Referenced to Full-Scale, PGA Gain = 0 dB) Dynamic Range (60 dB Input, THD+N Referenced to Full-Scale, PGA Gain = 6 dB)* Dynamic Range (60 dB Input, THD+N Referenced to Full-Scale, PGA Gain = +12 dB)* THD+N (1 dB Input Referenced to Full-Scale) Signal-to-Intermodulation Distortion (CCIF Method)* Offset Error (0 V Analog Input, PGA Gain = 0 dB)
*Guaranteed, not tested. Specifications subject to change without notice.
Typ 1.56 2.2 110 10 15
Max
Unit V rms V p-p k k pF
2.1
2.3
1.0 41.5
1.5 42.5
2.0 43.5
dB dB
85
90 90 90 90 80 1
85 5
dB dB dB dB dB % of FS
DAC TRANSMIT PATH
Min Digital-to-Analog Converter Dynamic Range (60 dB Input, THD+N Referenced to Full-Scale, Output Gain = 0 dB) THD+N (1 dB Input Referenced to Full-Scale) Signal-to-Intermodulation Distortion (CCIF Method)* Total Out-of-Band Energy (Measured from 0.555 × fS to 100 kHz)* DC Offset Programmable Gain/Attenuator Step Size (+12 dB to 34.5 dB, All Steps Tested) Output Attenuation Span Full-Scale Output Voltage AD1803 Tx Output (0 dBm) Pin Capacitance--AD1803 Tx Load Capacitance--AD1803 Tx
*Guaranteed, not tested. Specifications subject to change without notice.
Typ 85 75 80
Max
Unit dB dB dB dB mV dB dB V p-p pF pF
40 100 1.0 45.5 2.1 1.5 46.5 2.2 15 100 2.0 48 2.3
2
REV. 0
AD1803
MONITOR OUTPUT
Min Digital-to-Analog Converter Dynamic Range (60 dB Input, THD+N Referenced to Full-Scale, A-Weighted)* THD+N (Referenced to Full-Scale)* Programmable Gain/Attenuator Step Size (18 dB to +45 dB)* Output Attenuation Span*
NOTES *Guaranteed, not tested. Specifications subject to change without notice.
Typ 50 0.316 50
Max
Unit dB % dB dB dB
1 40 3.6
2.4
3.0 63
The table above assumes the G[4]/MOUT pin is loaded with a 1 k resistor in series with a parallel 4.7 k resistor and 100 nF capacitor combination tied to digital ground. This filter, with the output taken from the middle node, has a 1500 Hz corner to filter out high-frequency - noise, and generates an approximate 1 V p-p output when using a 5 V digital supply with the monitor output configured as first order (Bits MDM[1:0] set to 10 in Register 0 × 60 Bank 2) if the filter output load is greater than or equal to 20 k.
DIGITAL DECIMATION AND INTERPOLATION FILTERS 1
Min Pass-Band Edge (0.22 dB Point) Pass-Band (3.0 dB Point) Pass-Band Ripple Transition Band Stop-Band Edge2 Stop-Band Rejection (Plus 3 dB Roll-Off) Group Delay Group Delay Variation Over Pass Band 0 kHz to 4 kHz 0 kHz to 8 kHz Sample Rate
Typ
Max 0.445 × fS 0.490 × fS 0.2 0.555 × fS 21/fS 0.45 1.30 16
Unit Hz Hz dB Hz Hz dB s µs µs kHz
0.0 0.445 × fS 0.555 × fS 78.0
6.4
NOTES 1 Guaranteed, not tested. 2 The stop band repeats itself at multiples of 64 × fS, where fS is the sampling frequency. Thus the digital filter will attenuate to 78.0 dB or better across the frequency spectrum except for a range ± 0.555 × fS wide at multiples of 64 × fS. Specifications subject to change without notice.
TYPICAL SUPPLY CURRENT (For Most Common Modes of Operation)
Resource GPIO Weak Pull-Up Current per Pin While RESET Is Asserted: XTAL Off (All Down) XTALI Enabled: Nominal Power XTALI Enabled: Low Power and CLKOUT Pin Running
3.3 V ~100 <30.0 1.4 1.0 1.6
5.0 V ~140 µA <40.0 µA 2.4 mA 1.7 3.2
Register Writes To Enter Mode Default Settings After Power-On RESET Default Settings After Power-On RESET 5C:R34P4 = 1 5C:R34P4 = 1, 64b1:XTLP = 1 and 5C:CLKEA = 1
Assumption
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b b, c b, c c c c c, f c, f c, d, f c, e, f
While RESET Is Deasserted and Analog and Digital Codec in Full Power Mode SPORT and CLKOUT Active 2.6 6.4 Default Settings After Power-On RESET and XTAL in Low Power Mode 2.2 5.7 and 64b1:XTLP = 1 and CLKOUT Inactive (Low) 1.7 4.3 and 5C:CLKED = 0 and VREF Powered Up 1.9 4.5 and 3E:VPDN = 0 and ADC Enabled 7.3 12.4 and 3E:APDN = 0 or and DAC Enabled 8.2 13.7 and 3E:DPDN = 0 or and ADC + DAC Enabled 9.2 14.7 and 3E:APDN = DPDN = 0 or and ADC, DAC, + MON Enabled 9.3 14.9 and 3E:APDN = DPDN = 0, 5E : GPMON = 1 or and ADC, DAC, + MON Enabled 10.2 16.3 and 3E:APDN = DPDN = 0, 5E : GPMON = 1 REV. 0 3
AD1803
ASSUMPTIONS a Assumes all inputs are static (not switching) and all output loads are capacitive (nonresistive). b Excludes current drawn by CLKOUT pin board loading. c Assumes the serial interface is configured in AC'97 primary mode with 20 pF loads on pins SDATA_IN and BIT_CLK. Typical current will be approximately 0.8 mA less if the serial interface is configured in DSP mode with 20 pF loads on pins SYNC, BIT_CLK, and SDATA_IN (due to a lower BIT_CLK frequency). d Assumes a 20 pF load on Pin G[4]/MOUT. e Assumes the G[4]/MOUT pin is loaded with a 1 k resistor in series with a parallel 4.7 k resistor and 100 nF capacitor combination tied to digital ground. This filter, with the output taken from the middle node, has a 1500 Hz corner to filter out high-frequency - noise, and generates an approximate 1 V p-p output when using a 5 V digital supply with the Monitor output configured as first order (Bits MDM[1:0] set to 10 in Register 0 × 60 Bank 2) if the filter output load is greater than or equal to 20 k. f Assumes no DAC load. 0.6 mA should be added if a 600 load is used. g All currents in mA unless otherwise noted. Specifications subject to change without notice.
STATIC DIGITAL SPECIFICATIONS
Min High Level Input Voltage (VIH): Digital Inputs Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 0.5 mA Low Level Output Voltage (VOL), IOL = +0.5 mA Input Leakage Current Output Leakage Current
Specifications subject to change without notice.
Typ
Max 0.35 × DVDD 0.1 × DVDD +10 +10
Unit V V V V µA µA
0.65 × DVDD 0.9 × DVDD 10 10
POWER SUPPLY
Min Power Supply Range--Analog (3.3 V/5 V) AVDD Power Supply Range--Digital (3.3 V/5 V) DVDD Analog and Digital Supply Current--5 V Analog and Digital Supply Current--3.3 V Power Supply Rejection (100 mV p-p Signal @ 1 kHz) (At Both Analog and Digital Supply Pins, Both ADCs and DACs)
NOTES *Refer to table on typical supply current. Specifications subject to change without notice.
Typ
Max 3.6/5.25 3.6/5.25
Unit V V
3.0/4.75 3.0/4.75 * * 40
dB
CLOCK SPECIFICATIONS
Min Input Clock Frequency Recommended Clock Duty Cycle
Specifications subject to change without notice.
Typ 24.576 50
Max 32.768 55
Unit MHz %
12.288 45
4
REV. 0
AD1803
TIMING PARAMETERS (Guaranteed Over Operating Temperature Range and Supply Power)
Parameter Serial Port--AC'97 Mode RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Start-Up Delay SYNC Active High Pulsewidth (Warm RESET) SYNC Inactive to BIT_CLK Start-Up Delay (Warm RESET) BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK Propagation Delay BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low (MLNK Set) Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to HI-Z Delay (ATE Test Mode)
Symbol t R S T _L O W tRST2CLK tSYNC_HIGH tSYNC2CLK t C L K _P E R I O D t C L K _H I G H t C L K _L O W tSYNC_PERIOD tSETUP tHOLD tCO tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLOUT tS2_PDOWN tSETUP2RST tOFF
Min 1.0 162.8
Typ
Max
Unit µs ns µs ns MHz ns ps ns ns kHz µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.3 162.8 12.288 81.4 36.62 36.62 40.69 40.69 48.0 20.8 750 44.76 44.76
10.0 10.0 2 2 2 2 2 2 2 2 2 15 4 4 4 4 4 4 4 4 15 6 6 6 6 6 6 6 6 1000
25
Parameter Serial Port--DSP Mode RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Start-Up Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK Propagation Delay BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to HI-Z Delay (ATE Test Mode)
NOTES *Output jitter is directly dependent on crystal input jitter. Specifications subject to change without notice.
Symbol tRST_LOW tRST2CLK tCLK_PERIOD tSYNC_PERIOD tSETUP tHOLD tCO tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tSETUP2RST tOFF
Min 1.0 162.8
Typ
Max
Unit µs ns MHz ns ps kHz µs ns ns ns ns ns ns ns ns ns ns ns ns ns
4.096 244.14 750 8 125 10.0 10.0 2 2 2 2 2 2 2 2 15 4 4 4 4 4 4 4 4 15 6 6 6 6 6 6 6 6
25
REV. 0
5
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