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Details, datasheet, quote on part number:AD1816
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| Part: | AD1816 |
| Category: | Multimedia => Audio => Controllers => Management/Control |
| Description: | Single Chip Plug And Play Multimedia Audio Subsystem |
| Company: | Analog Devices |
| Datasheet: | Download AD1816 datasheet File size : 489 kB |
| Request For quote: | Find where to buy AD1816
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Datasheet text preview:
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FEATURES Compatible with Microsoft® PC 97 Logo Requirements Supports Applications Written for Windows® 95, Windows 3.1, Windows NT, SoundBlaster® Pro, AdLib®/OPL3® Stereo Audio 16-Bit Codec Internal 3D Circuit--PhatTM Stereo Phase Expander MPC Level-3 Mixer ISA Plug and Play Compatible 16-Bit Address Decode Dual Type F FIFO DMA Support MPU-401 Compatible MIDI Port Supports Wavetable Synthesizers Integrated Enhanced Digital Game Port Bidirectional DSP Serial Port Two I2S Digital Audio Serial Ports
SoundPort® Controller AD1816A
Integrated OPL3 Compatible Music Synthesizer Software and Hardware Volume Control Full-Duplex Capture and Playback Operation at Different Sample Rates Supports Up to Six Different Sample Rates Simultaneously 1 Hz Resolution Programmable Sample Rates from 4 kHz to 55.2 kHz Power Management Modes Operation from +5 V Supply Built-In 24 mA Bus Drivers 100-Lead PQFP and TQFP Package
FUNCTIONAL BLOCK DIAGRAM
MIDI_IN MIDI_OUT VOL_DN VOL_UP DATA XIRQ
CLK
SEL
A_X
B_X
AD1816A
HARDWARE VOLUME CONTROL AGC
MODEM/ LOGICAL DEVICE CONTROL
E2PROM CONTROL
SB PRO REGISTER
MPU-401
GAME PORT
MIC LINE
0dB/ 20dB
B_2 A_Y
A_1
B_1
A_2
B_Y
DRQ (X)
CD VID PHONE_IN
PGA
16-BIT A/D CONVERTER
FIFO
2
FORMAT
SYNTH
PLUG AND PLAY ISA BUS PARALLEL INTERFACE
SELECTOR
DSP SERIAL PORT
IRQ (X) PC_D (7:0) PC_A (15:0) AEN DACK (X) IOR IOW
2 M A
MUSIC SYNTHESIZER
MV L_OUT MV PHONE_OUT MV R_OUT
PHAT STEREO
M
A
16-BIT D/A CONVERTER
2 M A I2S SERIAL PORT (0) BCLK (0) LRCLK (0) SDATA (0) BCLK (1) LRCLK (1) SDATA (1) PCLKO
PHAT STEREO
M A SERIAL PORT INTERFACE
2
I2S SERIAL PORT (1)
G = GAIN A = ATTENUATE M = MUTE MV = MASTER VOLUME
OSCILLATORS
DIGITAL PLL
SDO
XTALO
XTALI
SoundPort is a registered trademark of Analog Devices, Inc. Phat is a trademark of Analog Devices, Inc. All other trademarks are the property of their respective holders.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997
SDFS
SCLK
SDI
FIFO
2
FORMAT
A M
G A M
G A M
G A M
G A M
G A M
AD1816A
PRODUCT OVERVIEW
The AD1816A SoundPort Controller is a single chip Plug and Play multimedia audio subsystem for concurrently processing multiple digital streams of 16-bit stereo audio in personal computers. The AD1816A maintains full legacy compatibility with applications written for SoundBlaster Pro and AdLib, while servicing Microsoft PC 97 application requirements. The AD1816A includes an internal OPL3 compatible music synthesizer, Phat
Stereo circuitry for phase expanding the analog stereo output, an MPU-401 UART, joystick interface with a built-in timer, a DSP serial port and two I2S serial ports. The AD1816A on-chip Plug and Play routine provides configuration services for all integrated logical devices. Using an external E2PROM allows the AD1816A to decode up to two additional external user-defined logical devices such as modem and CD-ROM.
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 11 HOST INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SERIAL INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AD1816A Chip Registers . . . . . . . . . . . . . . . . . . . . . . . . . 21 AD1816A Plug and Play Device Configuration Registers . . 22 Sound System Direct Registers . . . . . . . . . . . . . . . . . . . . . 23 Sound System Indirect Registers . . . . . . . . . . . . . . . . . . . 29 SB Pro; AdLib Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 38 MPU-401 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Game Port Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 APPENDIX A. PLUG AND PLAY INTERNAL ROM . . . . . . . . . . . . . . 40 PLUG AND PLAY KEY AND "ALTERNATE KEY" SEQUENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AD1816 AND AD1816A COMPATIBILITY . . . . . . . . . 42 USING AN EEPROM WITH THE AD1816 OR A D 1 8 1 6 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AD1816 FLAG BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 USING THE AD1816 WITHOUT AN EEPROM . . . . . 42 AD1816A FLAG BYTES . . . . . . . . . . . . . . . . . . . . . . . . 43 USING THE AD1816A WITHOUT AN EEPROM . . . . 44 MAPPING THE AD1816 EEPROM INTO THE AD1816A EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PIN MUXING IN THE AD1816 AND AD1816A . . . . . 45 PROGRAMMING EXTERNAL EEPROMS . . . . . . . . . 47 REFERENCE DESIGNS AND DEVICE DRIVERS . . . 47 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figures
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. PIO Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. PIO Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. DMA Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. DMA Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. Codec Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. DSP Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7. I2S Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . 7 Figure 8. Reset Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 9. Serial Interface Right-Justified Mode . . . . . . . . . . 17 Figure 10. Serial Interface I2S-Justified Mode . . . . . . . . . . . 17 Figure 11. Serial Interface Left-Justified Mode . . . . . . . . . . 17 Figure 12. DSP Serial Interface (Default Frame Rate) . . . . 20 Figure 13. DSP Serial Interface (User Programmed Frame Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 14. DSP Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 15. Codec Transfers . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16. Recommended Application Circuit . . . . . . . . . . 48 Figure 17. AD1816A Frequency Response Plots . . . . . . . . . 49
Tables
Table I. DSP Port Time Slot Map . . . . . . . . . . . . . . . . . . . Table II. Chip Register Diagram . . . . . . . . . . . . . . . . . . . . . Table III. Logical Devices and Compatible Plug and Play Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table IV. Internal Logical Device Configuration . . . . . . . . Table V. Sound System Direct Registers . . . . . . . . . . . . . . . Table VI. Codec Transfers . . . . . . . . . . . . . . . . . . . . . . . . . Table VII. Indirect Register Map and Reset/Default States . Table VIII. Sound System Indirect Registers . . . . . . . . . . . Table IX. SoundBlaster Pro ISA Bus Registers . . . . . . . . . . Table X. AdLib ISA Bus Registers . . . . . . . . . . . . . . . . . . . Table XI. MIDI ISA Bus Registers . . . . . . . . . . . . . . . . . . . Table XII. Game Port ISA Bus Registers . . . . . . . . . . . . . . Table XIII. AD1816 Pin Muxing . . . . . . . . . . . . . . . . . . . . Table XIV. AD1816A Pin Muxing . . . . . . . . . . . . . . . . . . .
18 21 22 23 23 27 30 31 38 39 39 39 45 46
2
REV. A
AD1816A
SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature Digital Supply (VDD) Analog Supply (VCC) Sample Rate (FS) Input Signal Frequency Audio Output Passband V IH V IL
25 5.0 5.0 48 1008 20 Hz to 20 kHz 5.0 0
°C V V kHz Hz V V
DAC Test Conditions 0 dB Attenuation Input Full Scale 16-Bit Linear Mode 100 k Output Load Mute Off Measured at Line Output ADC Test Conditions 0 dB Gain Input 4 dB Relative to Full Scale Line Input Selected 16-Bit Linear Mode
ANALOG INPUT
Parameter Full-Scale Input Voltage (RMS Values Assume Sine Wave Input) PHONE_IN, LINE, SYNTH, CD, VID MIC with +20 dB Gain (MGE = 1) MIC with 0 dB Gain (MGE = 0) Input Impedance* Input Capacitance*
PROGRAMMABLE GAIN AMPLIFIER--ADC
Min
Typ 1 2.83 0.1 0.283 1 2.83 17 15
Max
Units V rms V p-p V rms V p-p V rms V p-p k pF
Parameter Step Size (0 dB to 22.5 dB) (All Steps Tested) PGA Gain Range Span
Min
Typ 1.5 22.5
Max
Units dB dB
CD, LINE, MICROPHONE, SYNTHESIZER, AND VIDEO INPUT ANALOG GAIN/ATTENUATORS/MUTE AT LINE OUTPUT
Parameter CD, LINE, MIC, SYNTH, VID Step Size: (All Steps Tested) +12 dB to 34.5 dB Input Gain/Attenuation Range PHONE_IN Step Size 0 dB to 45 dB: (All Steps Tested) Input Gain/Attenuation Range
Min
Typ
Max
Units
1.5 46.5 3.0 45
dB dB dB dB
REV. A
3
AD1816A
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
Parameter Audio Passband Audio Passband Ripple Audio Transition Band Audio Stopband Audio Stopband Rejection Audio Group Delay Group Delay Variation Over Passband
ANALOG-TO-DIGITAL CONVERTERS
Min 0 0 . 4 × FS 0 . 6 × FS 82
Typ
Max 0 . 4 × FS ± 0.09 0 . 6 × FS 12/FS 0.0
Units Hz dB Hz Hz dB sec µs
Parameter Resolution Signal-to-Noise Ratio (SNR) (A-Weighted, Referenced to Full Scale) Total Harmonic Distortion (THD) (Referenced to Full Scale) Audio Dynamic Range (60 dB Input THD+N Referenced to Full-Scale, A-Weighted) Audio THD+N (Referenced to Full-Scale) Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L Read L) Line to MIC (Input LINE, Ground and Select MIC, Read ADC) Line to SYNTH Line to CD Line to VID Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error
DIGITAL-TO-ANALOG CONVERTERS
Min
Typ 16 82 0.011 79
Max 80 0.015 76.5
Units Bits dB % dB dB % dB dB dB dB dB dB dB % dB mV
79
82 76 82 95 95 95 95 95 0.019 74.5
22
80 80 80 80 80 ± 10 ±1 +15
Parameter Resolution Signal-to-Noise Ratio (SNR) (A-Weighted) Total Harmonic Distortion (THD) Audio Dynamic Range (60 dB Input THD+N Referenced to Full Scale, A-Weighted) Audio THD+N (Referenced to Full Scale) Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) Total Out-of-Band Energy (Measured from 0.6 × FS to 100 kHz at L_OUT and R_OUT)* Audible Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz at L_OUT and R_OUT)*
Min
Typ 16 83 0.006 85
Max 79 0.009 80.5
Units Bits dB % dB dB % dB dB % dB dB dB dB
79
82 0.013 78 95
0.017 75.5 ± 10 ± 0.5 80 45 75
MASTER VOLUME ATTENUATORS (L_OUT AND R_OUT, PHONE_OUT)
Parameter Master Volume Step Size (0 dB to 46.5 dB) Master Volume Output Attenuation Range Span Mute Attenuation of 0 dB Fundamental* 4
Min
Typ 1.5 46.5
Max
Units dB dB dB REV. A
80
AD1816A
DIGITAL MIX ATTENUATORS*
Parameter Step Size: I S (0), I S (1), Music, ISA Digital Mix Attenuation Range Span
ANALOG OUTPUT
2 2
Min
Typ 1.505 94.8
Max
Units dB dB
Parameter Full-Scale Output Voltage (at L_OUT, R_OUT, PHONE_OUT) Output Impedance* External Load Impedance* Output Capacitance* External Load Capacitance V REFX * VREFX Current Drive* VREFX Output Impedance* Master Volume Mute Click (Muted Analog Mixers), Muted Output Minus Unmuted Output at 0 dB
SYSTEM SPECIFICATIONS*
Min
Typ 2.8
Max 570
Units V p-p k pF pF V µA k mV
10 15 2.10 2.25 100 6.5 ±5 100 2.40
Parameter System Frequency Response Ripple (Line In to Line Out) Differential Nonlinearity Phase Linearity Deviation
STATIC DIGITAL SPECIFICATIONS
Min
Typ
Max 1.0 ±1 5
Units dB LSB Degrees
Parameter High Level Input Voltage (VIH) XTALI Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 8 mA Low Level Output Voltage (VOL), IOL = 8 mA Input Leakage Current Output Leakage Current
POWER SUPPLY
Min 2 2.4
Typ
Max
Units V V V V V µA µA
0.8 2.4 10 10 0.4 +10 +10
Parameter Power Supply Range--Analog Power Supply Range--Digital Power Supply Current Power Dissipation Analog Supply Current Digital Supply Current Analog Power Supply Current--Power-Down Digital Power Supply Current--Power-Down Analog Power Supply Current--RESET Digital Power Supply Current--RESET Power Supply Rejection (100 mV p-p Signal on Both Analog and Digital Supply Pins, Measured at ADC and Line Outputs)
CLOCK SPECIFICATIONS*
Min 4.75 4.75
Typ
Max 5.25 5.25 221 1105 51 170 2 24 0.2 10
Units V V mA mW mA mA mA mA mA mA dB
40
Parameter Input Clock Frequency Recommended Clock Duty Cycle Power-Up Initialization Time REV. A 5
Min 25
Typ 33 50
Max 75 500
Units MHz % ms
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