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Details, datasheet, quote on part number:AD1955YRSRL
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Datasheet text preview:
PRELIMINARY TECHNICAL DATA
a
FEATURES
High Performance Multibit DAC with SACD Playback
Preliminary Technical Data
APPLICATIONS
5V Power Supply Stereo Audio DAC System. Accepts 16/18/20/24-Bit Data Supports 24-Bits, 192kHz Sample Rate PCM Audio Data Supports SACD bit-stream and External Digital Filter Interface Accepts a Wide Range of PCM Sample Rates Including: 32kHz, 44.1kHz. 48kHz, 88.2kHz, 96kHz, and 192kHz Multibit Sigma Delta Modulator with "Perfect Differential Linearity Restoration" for Reduced Idle Tones and Noise Floor Data Directed Scrambling DAC - Least Sensitive to Jitter Supports SACD playback with "Bit Expansion" filter Differential Current Output for Optimum Performance 8.64 mA p-p Output Current with +3dB headroom in SACD mode 120 dB SNR/DNR (not muted) at 48KHz Sample Rate (A-Weighted Stereo) 123 dB SNR/DNR (Mono) -110 dB THD+N 110 dB Stopband Attenuation with +/-0.0002dB Passband Ripple 8 Times Oversampling Digital Filter On-chip Clickless Volume Control Supports SACD-Mute pattern detection Supports 64fs/128fs DSD SACD with phase modulation Internal Digital Filter pass-through for External Filter Master clock: 256fs,384fs,512fs,768fs Hardware and Software Controllable Clickless Mute Serial (SPI) Control for: Serial Mode, Number of Bits, Sample Rate, Volume, Mute, De-emphasis, Mono Mode Digital De-emphasis for 32, 44.1, 48 KHz Sample Rates Flexible Serial Data Port with Right-Justified, Left-Justified, I2S-Compatible and DSP Serial Port 28 Lead SSOP Plastic Package
AD1955
High-End DVD-Audio, SACD, CD, Home Theatre Systems, Automotive Audio Systems, Sampling Musical Keyboards, Digital Mixing Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEW The AD1955 is a complete high performance single-chip stereo digital audio playback system. It is comprised of a multibit sigma-delta modulator, high performance digital interpolation filters, and continuoustime differential current output DAC section. Other features include an on-chip clickless stereo attenuator, mute capability, programmed through an SPI-compatible serial control port. The AD1955 is fully compatible with all known DVD audio formats including 192kHz as well as 96kHz sample frequencies and 24-bits. It also is backwards compatible by supporting 50/15µs digital de-emphasis intended for "redbook" Compact Discs, as well as de-emphasis at 32kHz and 48kHz sample rate. The AD1955 has a very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSPs, SACD decoder, external digital filter, AES/EBU receivers and sample rate converters. The AD1955 can be configured in Left-justified, I2S, Right-Justified, or DSP serial port compatible modes. It can support MSB first, twoscompliment format, 16, 18, 20 and 24 bits in all standard PCM modes. Also the AD1955 has an interface for SACD playback and an external digital filter interface for use with an external digital interpolation filter or HDCD decoder. The AD1955 uses a +5 V power supply. It is fabricated on a single monolithic integrated circuit and is housed in a 28pin SSOP package for operation over the temperature range -400C to +1050C.
FUNCTIONAL BLOCK DIAGRAM
Master Clock Input Control Data Input 3 SPI Control Digital Filter Engine Multibit Sigma-Delta Modulator Digital Supply
Auto-Clock Divider 16/20/24Bit Audio Data / External Digital Filter Input 3/4 Serial Data Interface External Filter I/F DSD Filter
Voltage Reference I-DAC L-ch Differential Current Output I-DAC R-ch
M U X
S/H
NoiseShaped Scrambling
DSD Bitstream Input
4
RESET
MUTE
Analog Supply
ZERO Flags
Rev. PrF 3/18/2002
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 ©Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA AD1955
TEST CONDITIONS UNLESS OTHERWISE NOTED
Analog Supply Voltages (AVDD) Digital Supply Voltages (DVDD) Reference Current (Iref) Ambient Temperature Input Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Load Capacitance Load Impedance Input Voltage HI Input Voltage LO +5.0V +5.0V .960 mA 25OC 12.288 MHz 996.11 Hz 0 dB Full Scale 48 kHz 20 Hz to 20KHz 24 Bits 100 pF 47 k ohms 2.4 V .8 V Min Resolution Signal-to-noise Ratio (20 Hz to 20kHz) Differential Output (A-weighted, RMS) (Stereo) Differential Output (A-weighted, RMS) (Mono) Single-ended (Stereo) Dynamic Range (20 Hz to 20 kHz, -60 dB Input) Differential Output (A-weighted, RMS) (Stereo) Differential Output (A-weighted, RMS) (Mono) Single-ended (Stereo) Total Harmonic Distortion + Noise (Stereo) at 0 dBFS Analog Outputs Differential Output range (Full Scale) Output Capacitance at Each Output Pin Output bias current, Each Output Out-of-Band Energy (0.5XFs to 100 kHz) Reference Voltage DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Crosstalk (EIAJ method) Interchannel Phase Deviation Mute Attenuation De-emphasis Gain Error Typ 24 120 123 119 120 123 119 -108 8.64 100 -3.24 -90 2.39 +/-3 0.01 25 -125 +/- 0.1 -100 +/- 0.1 Max Units Bits dB dB dB dB dB dB dB mA p-p pF mA dB V % dB ppm/OC dB Degrees dB dB
ANALOG PERFORMANCE (See Figures ) Iref = .960 mA
NOTES: Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
DIGITAL I/O (-40oC to 105oC) Min Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH@VIH=2.4 V) Input Leakage (IIL@VIL=0.8 V) High Level Output Voltage (VOH) IOH = 1 mA Low Level Output Voltage (VOL) IOL = 1 mA Input Capacitance
Specifications subject to change without notice
Typ 0.8 10 10
Max V V uA uA V V pF
Units
2.0
2.4 0.4 20
-2-
Rev. PrF
PRELIMINARY TECHNICAL DATA AD1955
TEMPERATURE RANGE Min Specifications Guaranteed Functionality Guaranteed Storage
Specifications subject to change without notice
Typ 25 -40 -55
Max 105 125
Units
O O
C C O C
POWER Min Supplies Voltage, Digital Voltage, Analog Analog Current Analog Current - Reset Digital Current Digital Current - Reset Dissipation Operation - Both Supplies Operation - Analog Supply Operation - Digital Supply Power Supply Rejection Ratio 1kHz 300 mV p-p Signal at Analog Supply Pins 20kHz 300 mV p-p Signal at Analog Supply Pins
Specifications subject to change without notice
Typ 4.50 4.50 5 5 17 17 22 2 195 85 110 -77 -72
Max 5.50 5.50
Units V V mA mA mA mA mW mW mW dB dB
DIGITAL FILTER CHARACTERISTICS Sample Rate (kHz) Passband (kHz) 44.1 DC-20 48 DC-21.8 96 DC-39.95 192 DC-87.2
Specifications subject to change without notice
Stopband (kHz) 24.1-328.7 26.23-358.28 56.9-327.65 117-327.65
Stopband Attenuation (dB) 110 110 115 95
Passband Ripple (dB) +/- 0.0002 +/- 0.0002 +/- 0.0005 +0/-0.04 (DC-21.8 kHz) +0/-0.5 (DC-65.4 kHz) +0/-1.5 (DC-87.2 kHz)
GROUP DELAY Chip Mode INT8x Mode INT4x Mode INT2x Mode
Specifications subject to change without notice
Group Delay Calculation 5553/(128 × FS) 5601/(64 × FS) 5659/(32 × FS)
Fs 48kHz 96kHz 192kHz
Group Delay 903.8 911.6 921
Units µs µs µs
DIGITAL TIMING (Guaranteed over -40°C to 85°C, AVDD = DVDD = +5.0 V +/- 10%) tDMP tDML tDMH tDBH tDBL tDBP tDLS tDLH tDDS tDDH tDMP tDML tDMH tCLS tCLH tCDS tCDH tRSTL MCLK Period (FMCLK = 256*FLRCLK) MCLK LO Pulse Width (all modes) MCLK HI Pulse Width (all modes) BCLK HI Pulse Width BCLK LO Pulse Width BCLK Period LRCLK Setup LRCLK Hold (DSP Serial Port mode only) SDATA Setup SDATA Hold CCLK Period CCLK LO Pulse Width CCLK HI Pulse Width CLATCH Setup CLATCH Hold CDATA Setup CDATA Hold RST LO Pulse Width Min 54 0.4 X tDMP 0.4 X tDMP 20 20 60 20 5 5 10 50 15 15 10 10 10 10 15 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Specifications subject to change without notice.
Rev. PrF
-3-
PRELIMINARY TECHNICAL DATA AD1955
ABSOLUTE MAXIMUM RATINGS*
Min DVDD to DGND AVDD to AGND Digital Inputs Analog Outputs AGND to DGND Reference Voltage Soldering -0.3 -0.3 DGND - 0.3 AGND - 0.3 -0.3 6 6 DVDD + 0.3 AVDD + 0.3 0.3 (AVDD + 0.3)/2 +300 10 Max Units V V V V V
O
PACKAGE CHARACTERISTICS
Min OJA (Thermal Resistance [Junction-to-Ambient]) OJC (Thermal Resistance [Junction-to-Case]) Typ 109.0 39.0 Max
O
Units C/W C/W
O
C sec
* Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD1955YRS AD1955YRSRL Temperature -40 OC to +105 OC -40 OC to +105 OC Package Description 28-Lead SSOP 28-Lead SSOP Package Option* RS-28 RS-28 on 13" Reels
*RS = Shrink Small Outline
PIN CONFIGURATION
DVDD EF_WCLK/LRCLK EF_BCLK/BCLK EF_LDATA/SDATA EF_RDATA DSD_SCLK DSD_LDATA DSD_RDATA DSD_PHASE 1 2 3 4 5 6 7 8 9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DGND MCLK CCLK CLATCH CDATA PD/RST MUTE ZEROL ZEROR AGND IOUTL+ IOUTLFILTB AVDD
AGND 10 IOUTR+ 11 IOUTR- 12 FILTR 13 IREF 14
CAUTION
ESD (Electrostatic discharge) sensitive device. Electrostatic charges as high as 400 V readily accumulate on the human body and Test equipment and can discharge without detection. Although the AD1959 features proprietary ESD protection circuitry, permanent Damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-4-
Rev. PrF
PRELIMINARY TECHNICAL DATA AD1955
PIN FUNCTION DESCRIPTIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 I/O Input Input Input Input I/O Input Input I/O Output Output Output Pin Name DVDD EF_WCLK/LRCLK EF_BCLK/BCLK EF_LDATA/SDATA EF_RDATA DSD_SCLK DSD_LDATA DSD_RDATA DSD_PHASE AGND IOUTR+ IOUTRFILTR IREF AVDD FILTB IOUTLIOUTL+ AGND ZEROR ZEROL MUTE PD/RST Description Digital Power Supply Connected to Digital 5V supply. Word Clock in External Filter mode. Left/Right Clock input for input data in PCM mode. Bit Clock input in External Filter mode. Bit Clock input for input data in PCM mode. 8fs or 4fs L-ch Data input in External filter mode. Data should be MSB first two's complement format. In the PCM mode, serial input, MSB first, containing two channels(left and right) of 16 to 24bit two's complement 1fs data. 8fs or 4fs R-ch Data input in External filter mode. Data should be MSB first two's complement format. Not used in PCM mode Shift clock input for DSD data. This clock should be 64x44.1kHz, 2.8224MHz or 128x44.1kHz, 5.6448MHz in normal mode or 128x44.1kHz, 5.6448MHz or 256x44.1kHz, 11.2896MHz in phase mode. DSD Left channel data input DSD Right channel data input DSD phase reference signal. This clock should be 64x44.1kHz, 2.8224MHz. If not used this pin should be connected Low. Analog Ground Right Channel Positive analog output. Right Channel Negative analog output. Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference with parallel 10uF and 0.1uF capacitors to AGND Connection point for external bias resistor. Analog power supply Connected to Analog 5V supply Filter Capacitor Connection with parallel 10uF and 0.1uF capacitors to AGND Left Channel Negative analog output. Left Channel Positive analog output. Analog Ground Right Channel Zero Flag Output. This pin goes high when the right channel has no signal input or the DSD mute pattern is detected. Left Channel Zero Flag Output. This pin goes high when the left channel has no signal input or the DSD mute pattern is detected. Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation. Power down/Reset. The AD1955 is placed in a reset state and the digital circuitry is powered down when this pin is held LO. The AD1955 is reset on the rising edge of this signal. The serial control port registers are reset to the default values. Connect HI for normal operation. Serial control input, MSB first, containing 16 bits of unsigned data. Used for specifying control information and channel-specific attenuation. Latch Input for control data. Control Clock input for control data. Control input data must be valid on the rising edge of CCLK. CCLK may be continuous or gated. Master Clock Input. Connect to an external clock source. Digital Ground
Output Output Output Output Output Input Input
24 25 26 27 28
Input Input Input Input
CDATA CLATCH CCLK MCLK DGND
Rev. PrF
-5-
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