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Details, datasheet, quote on part number:AD1959
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Datasheet text preview:
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FEATURES 5 V Stereo Audio DAC System Accepts 16-Bit/20-Bit/24-Bit Data Supports 24 Bits, 192 kHz Sample Rate Accepts a Wide Range of Sample Rates Including: 3 2 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz Multibit Sigma-Delta Modulator with Data Directed Scrambling Single-Ended Output for Easy Application 94 dB THD + N 108 dB SNR and Dynamic Range 75 dB Stopband Attenuation Clickless Volume Control Hardware and Software Controllable Clickless Mute Serial (SPI) Control for: Serial Mode, Number of Bits, Sample Rate, Volume, Mute, De-Emphasis and Output Phase Digital De-Emphasis Processing for 32 kHz, 44.1 kHz, and 48 kHz Sample Rates Programmable Dual Fractional-N PLL Clock Generator 27 MHz Master Clock Input/Oscillator Generated System Clocks SCLK0: 33.8688 MHz SCLK1: 384/256 fS (32 kHz/44.1 kHz/48 kHz/88.2 kHz/ 96 kHz) SCLK2: 512 f S (32 kHz/44.1 kHz/48 kHz/88.2 kHz/ 96 kHz)/22.5792 MHz Better than 100 ps RMS Clock Jitter Flexible Serial Data Port with Right-Justified, LeftJustified, I2S-Compatible, and DSP Serial Port Modes 28-Lead SSOP Plastic Package
PLL/Multibit - DAC AD1959
APPLICATIONS DVD, CD, Home Theater Systems, Automotive Audio Systems, Sampling Musical Keyboards, Digital Mixing Consoles, Digital Audio Effects Processors PRODUCT OVERVIEW
The AD1959 is a complete high-performance single-chip stereo digital audio playback system. It is comprised of a multibit sigmadelta modulator, digital interpolation filters, and analog output drive circuitry with an on-board dual PLL clock generator. Other features include an on-chip stereo attenuator and mute, programmed through an SPI-compatible serial control port. The AD1959 is fully compatible with all known DVD formats including 96 kHz and 192 kHz sample frequencies and 24 bits. It also is backwards-compatible by supporting 50 µs/15 µs digital de-emphasis for "redbook" compact discs, as well as de-emphasis at 32 kHz and 48 kHz sample rates. The AD1959 has a simple but flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers, and sample rate converters. The AD1959 can be configured in left-justified, I2S, right-justified, or DSP serial-port-compatible modes. It can support 16, 20, and 24 bits in all modes. The AD1959 accepts serial audio data in MSB first, two's-complement format, and operates from a single 5 V power supply. It is fabricated on a single monolithic integrated circuit and housed in a 28-lead SSOP package for operation over the temperature range 40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
XIN XOUT MCLK LOOP FILTERS 2 CLOCK OUTPUTS 3 CONTROL DATA INPUT 3
AD1959
OSC
PLL CIRCUIT
SERIAL CONTROL INTERFACE
VOLTAGE REFERENCE
ATTEN/MUTE 16-/20-/24BIT DIGITAL DATA INPUT SERIAL DATA INTERFACE ATTEN/MUTE
8 FS INTERPOLATOR
MULTIBIT SIGMA-DELTA MODULATOR
DAC
OUTPUT BUFFER
L ANALOG OUTPUTS
3
8 FS INTERPOLATOR
MULTIBIT SIGMA-DELTA MODULATOR
DAC
OUTPUT BUFFER
R
2 RESET MUTE ZERO FLAG PLL SUPPLY
2 DIGITAL SUPPLY
3 ANALOG SUPPLY
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD1959SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD) 5.0 V Ambient Temperature 25 °C Input Clock 12.288 MHz Input Signal 996.11 Hz 0.5 dB Full Scale Input Sample Rate 48 kHz Measurement Bandwidth 20 Hz to 20 kHz Word Width 20 Bits Load Capacitance 100 pF Load Impedance 47 k Input Voltage HI 3.5 V Input Voltage LO 0.8 V
ANALOG PERFORMANCE
Min Resolution Signal-to-Noise Ratio (20 Hz to 20 kHz) No Filter (Stereo) With A-Weighted Filter (Stereo) Dynamic Range (20 Hz to 20 kHz, 60 dB Input) No Filter (Stereo) With A-Weighted Filter (Stereo) Total Harmonic Distortion + Noise (Stereo) PLL Performance Master Clock Input Frequency Generated System Clocks SCLK0 SCLK1 SCLK2 Jitter (SCLK0 and SCLK1) Analog Outputs Single-Ended Output Range (± Full Scale) Output Capacitance at Each Output Pin VREF (FILTR) Gain Error Interchannel Gain Mismatch Gain Drift DC Offset Out-of-Band Energy (0.5 × fS to 100 kHz) Interchannel Crosstalk (EIAJ Method) Interchannel Phase Deviation De-Emphasis Gain Error
Typ 24 105 108 105 108 94 27 33.8688 12.288 22.5792 85 3.17
Max
Unit Bits dB dB dB dB dB MHz MHz MHz MHz ps rms V p-p pF V % dB p p m /° C mV dB dB Degrees dB
101
91
125
2.34 5 0.15 25
2.39 ± 2.0 ± 0.015 150 5 120 ± 0.1
2 2.44 +5 +0.15 250 +15 90 ± 0.1
NOTES Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Specifications subject to change without notice.
DIGITAL I/O (40°C to +105°C )
Min Input Voltage HI (VIH) Except XIN Input Voltage HI (VIH) XIN Input Voltage LO (VIL) Input Leakage (IIH @ VIH = 2.4 V) Input Leakage (IIL @ VIL = 0.8 V) High Level Output Voltage (VOH) IOH = 1 mA Low Level Output Voltage (VOL) IOL = 1 mA Except XOUT Low Level Output Voltage (VOL) IOL = 1 mA XOUT Input Capacitance
Specifications subject to change without notice.
Typ
Max
Unit V V V µA µA V V V pF
2.2 2.7 0.8 10 10 2.0 0.4 1.2 20
2
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AD1959
TEMPERATURE RANGE
Min Specifications Guaranteed Functionality Guaranteed Storage 40 55
Typ 25
Max +105* +150
Unit °C °C °C
NOTES *105°C ambient guaranteed for a 4-layer board, two 1 oz. planes, two 2 oz. signal layers. Derate to 85 °C for 2-layer board, 2 oz. layers. Specifications subject to change without notice.
POWER
Min Supplies Voltage, Analog Digital PLL Analog Current Digital Current PLL Current Dissipation Operation All Supplies Operation Analog Supply Operation Digital Supply Operation PLL Supply
Specifications subject to change without notice.
Typ 5 36 28 27 455 180 140 135
Max 5.50 42 34 32 540
Unit V mA mA mA mW mW mW mW
4.50
DIGITAL FILTER CHARACTERISTICS
Sample Rate (kHz) 44.1 48 96 192
Pass Band (kHz) DC20 DC21.8 DC39.95 DC87.2
Stop Band (kHz) 24.1328.7 26.23358.28 56.9327.65 117327.65
Stopband Attenuation (dB) 75 75 75 60
Pass-Band Ripple (dB) ± 0.0002 ± 0.0002 ± 0.0005 0/0.04 (DC21.8 kHz) 0/0.5 (DC65.4 kHz) 0/1.5 (DC87.2 kHz)
Specifications subject to change without notice.
GROUP DELAY
Chip Mode INT8× Mode INT4× Mode INT2× Mode
Group Delay Calculation 2 4 . 6 2 5 / fS 15.75/fS 14/fS
fS 48 kHz 96 kHz 192 kHz
Group Delay 513 164 72.91
Unit µs µs µs
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed over 40°C to +105°C, AVDD = DVDD = 5.0 V ± 10%)
Min tDMP tDML tDMH tDBH tDBL tDBP tDLS tDLH tDDS tDDH tRSTL MCLK Period (FMCLK = 256 × FLRCLK) MCLK LO Pulsewidth (All Modes) MCLK HI Pulsewidth (All Modes) BCLK HI Pulsewidth BCLK LO Pulsewidth BCLK Period LRCLK Setup LRCLK Hold (DSP Serial Port Mode Only) SDATA Setup SDATA Hold RST LO Pulsewidth 54 15 10 7 12 60 20 20 15 10 15
Unit ns ns ns ns ns ns ns ns ns ns ns
Specifications subject to change without notice.
REV. 0
3
AD1959
ABSOLUTE MAXIMUM RATINGS* PACKAGE CHARACTERISTICS
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V Digital Inputs . . . . . . . . . . DGND 0.3 V to DVDD + 0.3 V Analog Inputs . . . . . . . . . . AGND 0.3 V to AVDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . 0.3 V to + 0.3 V Reference Voltage . . . . . . . . . . . . . . . . . . . . . (AVDD + 0.3)/2 Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
JA (Thermal Resistance) Junction-to-Ambient 109.0°C/W Typ (2-Layer Board) JA (Thermal Resistance) Junction-to-Ambient 78.58°C/W Typ (4-Layer Board--2 Signal, 2 Planes) JA (Thermal Resistance) Junction-to-Case 39.0°C/W Typ
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1959 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model AD1959YRS AD1959YRSRL EVAL-AD1959EB
Temperature 40°C to +105 °C 40°C to +105 °C
Package Description 28-Lead Small Outline Package 28-Lead Small Outline Package Evaluation Board
Package Option RS-28 RS-28 on 13" Reels
PIN CONFIGURATION
CCLK 1 CLATCH 2 RESET 3 LRCLK 4 BCLK 5 SDATA 6 DVDD 7
28 CDATA 27 MUTE 26 ZERO 25 FILTB 24 AVDD
AD1959
23 OUTL
TOP VIEW 22 AGND1 DGND 8 (Not to Scale) 21 FLTR SCLK0 9 MCLK 10 XOUT 11 XIN 12 SCLK1 13 SCLK2 14
20 OUTR 19 AGND0 18 LF1 17 LF0 16 PGND 15 PVDD
4
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AD1959
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3
Input/Output I I I
Mnemonic CCLK CLATCH RESET
Description Control Clock Input for Control Data. Control input data must be valid on the rising edge of CCLK. CCLK may be continuous or gated. Latch Input for Control Data. Reset. The AD1959 is placed in a reset mode when this pin is held LO. The serial control port registers are reset to their default values. Set HI for normal operation. Left/Right Clock Input for Input Data. Must run continuously. Bit Clock Input for Input Data. Need not run continuously; may be gated or used in a burst fashion. Serial input, MSB first, containing two channels of 16/20/24 bits of two'scomplement data per channel. Digital Power Supply Connect to Digital 5 V Supply. Digital Ground. 33.8688 MHz Clock Output. 27 MHz Master Clock Output/256 fS DAC Clock Input. 27 MHz Crystal Oscillator Output. 27 MHz Crystal Oscillator/External Clock Input. 256/384 fS Output. 512 fS/22.5792 MHz Output. PLL Power Supply. Connect to PLL 5 V Supply. PLL Ground. PLL0 Loop Filter. PLL1 Loop Filter. Analog Ground. Right Channel Positive Line Level Analog Output. Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference with parallel 10 µF and 0.1 µF capacitors to AGND. Analog Ground. Left Channel Line Level Analog Output. Analog Power Supply. Connect to Analog 5 V Supply. Filter Capacitor Connection, Connect 10 µF Capacitor to AGND. Zero Flag Output. This pin goes HI when both channels have zero signal input for more than 1024 L/R Clock Cycles. Mute. Assert HI to Mute Both Stereo Analog Outputs. Deassert LO for normal operation. Serial control input, MSB first, containing 16 bits of unsigned data per channel.
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
I I I I I O I/O O I O O
LRCLK BCLK SDATA DVDD DGND SCLK0 MCLK XOUT XIN SCLK1 SCLK2 PVDD PGND LF0 LF1 AGND0 OUTR FILTR AGND1 OUTL AVDD FILTB ZERO MUTE CDATA
O O I O
O I I
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