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Details, datasheet, quote on part number:AD1980JST
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Datasheet text preview:
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FEATURES AC '97 2.3 COMPATIBLE FEATURES 6 DAC Channels for 5.1 Surround S/PDIF Output Integrated Stereo Headphone Amplifier Variable Rate Audio Double Rate Audio (fS = 96 kHz) Greater than 90 dB Dynamic Range 20-Bit PCM DACs Line-Level Mono "Phone" Input High Quality CD Input Selectable MIC Input with Preamp AUX and Line_In Stereo Inputs External Amplifier Power-Down Control Power Management Modes 48-Lead LQFP Package
AC '97 SoundMAX Codec AD1980
®
ENHANCED FEATURES Integrated Parametric Equalizer Stereo MIC Preamp Support Integrated PLL for System Clocking Variable Sample Rate 7 kHz to 96 kHz Jack Sense (Auto Topology Switching) Software Controlled VREF_OUT for MIC Bias Software Enabled Outputs for Jack Sharing Auto Down-Mix and Channel Spreading Modes
FUNCTIONAL BLOCK DIAGRAM
VREFOUT VREF VOLTAGE REFERENCE XTL_OUT XTL_IN SPDIF
AD1980
MC1
MIC PREAMP G G
G
MC2 PHONE_IN CD_L CD_GND CD_R AUX_L AUX_R LINE_IN_L LINE_IN_R CD DIFF AMP
2CMIC
CODEC CORE
PCM L/R ADC RATE
SPDIF TX
MS
PLL
RECORD SELECTOR
ID0
G
M
16-BIT - ADC 16-BIT - ADC ID1
G
M
PCM LFE DAC RATE
RESET
LFE_OUT
MZ
A
SPRD
M
G
AC '97 INTERFACE
20-BIT - DAC
DAC SLOT LOGIC
SYNC
CENTER_OUT
MZ
A
SPRD
M
G
20-BIT - DAC
GA M M M GA M
GA M GA M GA M
GA M GA M
GA M M M
G = GAIN A = ATTENUATION M = MUTE Z = HIGH Z PCM FRONT DAC RATE
BITCLK
LINE_OUT_L
MZ MZ MZ
A
BYPASS
MONO_OUT LINE_OUT_R
A
LOSEL
EQ COEF STORAGE
LOSEL
SDATA_OUT
EQ
SDATA_IN
A
M M M M
HPSEL
G G
20-BIT - DAC 20-BIT - DAC 20-BIT - DAC 20-BIT - DAC PCM SURR DAC RATE
BYPASS
SURR_OUT_L/ HP_OUT_L
HP
M
A
HPSEL
EQ AC '97 CONTROL REGISTERS
G
SURR_OUT_R/ HP_OUT_R
HP
M
M M G
A
ANALOG MIXING CONTROL LOGIC
EAPD
JS0
JS1
EAPD
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2002 Analog Devices, Inc. All rights reserved.
AD1980SPECIFICATIONS
STANDARD TEST CONDITIONS, UNLESS OTHERWISE NOTED DAC Test Conditions
Temperature Digital Supply (DVDD) Analog Supply (AVDD) Sample Rate (fS) Input Signal Analog Output Pass Band
2 5°C 3.3 V 5.0 V 48 kHz 1008 Hz 20 Hz to 20 kHz
Calibrated 3 dB Attenuation Relative to Full Scale 0 dB Input 10 k Output Load LINE_OUT, MONO_OUT, CENTER_OUT, and LFE_OUT 32 Output Load (HP_OUT)
ADC Test Conditions
Calibrated 0 dB Gain Input 3.0 dB Relative to Full Scale Parameter ANALOG INPUT Input Voltage (rms Values Assume Sine Wave Input) LINE_IN, CD, AUX, PHONE_IN MIC_IN with 30 dB Preamp MIC_IN with 20 dB Preamp MIC_IN with 10 dB Preamp MIC_IN with 0 dB Gain Input Impedance* Input Capacitance* MASTER VOLUME Step Size (Line Out, Mono Out, Surround Out, Center, LFE) Output Attenuation Range Span* Mute Attenuation of 0 dB Fundamental* PROGRAMMABLE GAIN AMPLIFIER--ADC Step Size (0 dB to 22.5 dB) PGA Gain Range Span ANALOG MIXER--INPUT GAIN/AMPLIFIERS/ATTENUATORS Signal-to-Noise Ratio (SNR) CD to LINE_OUT LINE, AUX, PHONE, to LINE_OUT* MIC1 or MIC2 (Note: MIC Gain of 0 dB) to LINE_OUT* Step Size All Mixer Inputs Input Gain/Attenuation Range: All Mixer Inputs DIGITAL DECIMATION AND INTERPOLATION FILTERS* Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Rejection Group Delay Group Delay Variation over Pass Band 0 0.4 0.6 74 fS fS 1 6 / fS 0 Min Typ Max Unit
1 2.83 0.032 0.089 0.1 0.283 0.316 0.894 1 2.83 20 5 1.5 46.5
7.5
V rms V p-p V rms V p-p V rms V p-p V rms V p-p V rms V p-p k pF dB dB dB dB dB
80 1.5 22.5
90 90 90 1.5 46.5 0 . 4 fS ± 0.09 0 . 6 fS
dB dB dB dB dB Hz dB Hz Hz dB sec µs
2
REV. 0
AD1980
Parameter ANALOG-TO-DIGITAL CONVERTERS Resolution Total Harmonic Distortion (THD) AVDD = 5.0 V Dynamic Range (60 dB Input THD + N Referenced to FS, A-Weighted) AVDD = 5.0 V Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) LINE_IN to Other Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error* (0 dB Gain, HPF On) DIGITAL-TO-ANALOG CONVERTERS Resolution Total Harmonic Distortion (THD), LINE_OUT, AVDD = 5.0 V Total Harmonic Distortion (THD), HP_OUT, AVDD = 5.0 V Total Harmonic Distortion (THD), CENTER/LFE, AVDD = 5.0 V Dynamic Range (60 dB Input THD + N Referenced to FS A-Weighted) AVDD = 5.0 V Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk (Input L, Zero R, Read LINE_OUT_R; Input R, Zero L, Read LINE_OUT_L, 10 k Load)* Total Audible Out-of-Band Energy* (Measured from 0.6 fS to 20 kHz) ANALOG OUTPUT Full-Scale Output Voltage; LINE_OUT/MONO_OUT, CENTER_OUT, LFE_OUT Output Impedance* External Load Impedance* (LINE_OUT, CENTER_OUT/LFE_OUT, MONO_OUT) Output Capacitance* External Load Capacitance* Full-Scale Output Voltage; HP_OUT (0 dB Gain) External Load Impedance*; HP_OUT V REF VREF_OUT (VREFH = 0) VREF_OUT (VREFH = 1) VREF_OUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output) STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH): Digital Inputs Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 2 mA Low Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current POWER SUPPLY Power Supply Range; Analog (AVDD) Power Supply Range; Digital (DVDD) Power Dissipation 5 V/3.3 V Analog Supply Current 5 V (AVDD) Digital Supply Current 3.3 V (DVDD) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs)
*Guaranteed but not tested. Specifications subject to change without notice.
Min
Typ 16 78 82 84 95 90
Max
Unit Bits dB dB dB
90 85 ± 10 ± 0.5 ± 10
dB dB % dB mV Bits dB dB dB dB
20 90 73 82.5 90 88 ± 10 ± 0.7 80 40
dB % dB dB dB
1 2.83 800 10 15 100 1 32 2.05 2.25 2.25 3.65 ±5 0.65 0.9 10 10 4.75 3.15 563 70 53 40 DVDD 0.35 DVDD 0.1 DVDD +10 +10 5.25 3.45 DVDD 2.45
V rms V p-p k pF pF V rms V V V mA mV V V V V µA µA V V mW mA mA dB
5
REV. 0
3
AD1980
Parameter POWER-DOWN STATES Fully Active ADC FRONT DAC SURROUND DAC CENTER/LFE DAC ADC + ALL DACs Mixer ADC + Mixer ALL DACs + Mixer ADC + ALL DACs + Mixer Standby Headphone Standby
2
P R [ K : I ]1 000 000 000 010 101 111 000 000 111 111 111 000
P R [ 6 : 0 ]1 000 0000 000 0001 000 0010 000 0000 000 0000 000 0011 000 0100 000 0101 000 0110 000 0111 011 1111 100 0000
DVDD Typ 53 44 46 46 46 12 52 45 31 12 0 52
AVDD Typ 70 66 61 61 61 33 44 39 14 8 0 65
Unit mA mA mA mA mA mA mA mA mA mA mA mA
NOTES 1 PR bits are controlled in Reg. 2Ah and 26h 2 Values presented with V REFOUT loaded. Specifications subject to change without notice.
Parameter CLOCK SPECIFICATIONS Input Clock Frequency (XTAL Mode or Clock Oscillator) Input Clock Frequency (Reference Clock Mode) Input Clock Frequency (USB Clock Mode) Recommended Clock Duty Cycle
Guaranteed but not tested. Specifications subject to change without notice.
*
Min
*
Typ 24.576 14.31818 48.000 50
Max
Unit MHz MHz MHz %
40
60
TIMING PARAMETERS (Guaranteed over Operating Temperature Range)
Parameter RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Startup Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Frequency Accuracy BIT_CLK Period BIT_CLK Output Jitter1, 2 BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to RESET Inactive (SYNC, SDATA_OUT) Rising Edge of RESET to Hi-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from BIT_CLK Rising
NOTES 1 Guaranteed but not tested. 2 Output jitter directly dependent on crystal input jitter. Specifications subject to change without notice.
Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tH O L D tRISECLK tFALLCLK tRISESYNC tFALLSYNC t RISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF
Min 162.8
Typ 1.0
Max 400,000
Unit µs ns µs µs ns MHz ppm ns ps ns ns kHz µs ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns ns
1.3 19.5 162.8 12.288 81.4 750 40 39.7 48.0 20.8 4 3 2 2 2 2 2 2 2 2 0 15 4 4 4 4 4 4 4 4 6 6 6 6 6 6 6 6 1.0 25 15 50 15 41.7 41.4 1.0
4
REV. 0
AD1980
tRST2CLK tRST_LOW
RESET
tTRI2ACTV
BIT_CLK
tTRI2ACTV
SDATA_IN
Figure 1. Cold Reset Timing (Codec is Supplying the Bit_CLK Signal)
tSYNC_HIGH
SYNC
tSYNC2CLK
BIT_CLK
Figure 2. Warm Reset Timing
tCLK_LOW
SYNC
BIT_CLK
SLOT 1
SLOT 2
tCLK_HIGH tCLK_PERIOD
BIT_CLK
SDATA_OUT
tSYNC_LOW
SYNC
WRITE TO 0 26
DATA PR4
tS2_PDOWN
SDATA_IN
tSYNC_HIGH tSYNC_PERIOD
BIT_CLK NOT TO SCALE
Figure 5. AC-Link Low Power Mode Timing
tCO tSETUP
Figure 3. Clock Timing
BIT_CLK
tRISECLK
tFALLCLK
BIT_CL
VIH
VIL
SYNC
SDATA_O
tRISESYNC
tFALLSYNC
SDATA_I SYN
VOH VOL
SDATA_IN
tHOLD tRISEDIN tFALLDIN
Figure 6. AC-Link Low Power Mode Timing
RESET
SDATA_OUT
tRISEDOUT
tFALLDOUT
SDATA_OUT
Figure 4. Signal Rise and Fall Times
tSETUP2RST
SDATA_IN, BIT_CLK, EAPD, SPDIF_OUT AND DIGITAL I/O Hi-Z
tOFF
Figure 7. ATE Test Mode
REV. 0
5
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