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Details, datasheet, quote on part number:AD1981AJST
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Datasheet text preview:
a
AC '97 2.2-COMPLIANT CODEC FEATURES S/PDIF Output, 20 Bits Data Format, Supporting 48 kHz and 44.1 kHz Sample Rates Integrated Stereo Headphone Amplifier Variable Sample Rate Audio External Audio Power-Down Control Greater than 90 dB Dynamic Range 16-Bit Stereo Full-Duplex Codec 20-Bit DAC Input Three Analog Line-Level Stereo Inputs for LINE-IN, AUX, and CD Mono Line-Level Phone Input Mono MIC Input with Built-In Programmable Preamp
AC `97 SoundMAX Codec AD1981A
High Quality CD Input with Ground Sense Mono Output for Speakerphone or Internal Speaker Power Management Support 48-Lead LQFP Package ENHANCED FEATURES Built-in Digital Equalizer Function for Optimized Speaker Sound Full Duplex Variable Sample Rates from 7040 Hz to 48 kHz with 1 Hz Resolution Jack Sense Pins Provide Automatic Output Switching Software-Programmed V REFOUT Output for Microphone Bias and External Power Amp Split Power Supplies: 3.3 V Digital and 5 V Analog Multiple Codec Configuration Options
®
FUNCTIONAL BLOCK DIAGRAM
VREF VREFOUT XTL_OUT XTL_IN ID1 ID0
AD1981A
MIC_IN AUX PHONE_IN CD_L CD_GND CD_R LINE_IN CD DIFF AMP
MIC PREAMP G VREF SELECTOR G XTAL OSCILLATOR LINK PORT/ ID SELECT
A/D SAMPLE RATE GENERATOR G G M M 16-BIT - A/D CONVERTER 16-BIT - A/D CONVERTER 16-BIT - A/D CONVERTER 16-BIT - A/D CONVERTER 20-BIT - D/A CONVERTER 20-BIT - D/A CONVERTER
PLL CLOCK GENERATOR
G G M HP_OUT_L HP M A M LINE_OUT_L M A SELECTOR GA GA M M M GA M M GA GA M M M GA GA GA
M
D/A SAMPLE RATE GENERATOR AC '97 SERIAL INTERFACE
M GA
SPKR EQ SPKR EQ
GA
EQ COEFF STORAGE
MONO_OUT
M
A
AC '97 CONTROL REGISTERS M ANALOG MUTE CONTROL LOGIC M SPDIF
LINE_OUT_R
M
A
HP_OUT_R
HP
M
A
JACK SENSE
EAPD
KEY: G = GAIN A = ATTENUATE M = MUTE
JS0
JS1
EAPD
SPDIF
SoundMAX is a registered trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
AC '97 LINK SIGNALS
AD1981ASPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature Digital Supply (DVDD) Analog Supply (VDD) Sample Rate (FS) Input Signal Analog Output Pass Band V IH V IL VIH (ID0, ID1) VIL (ID0, ID1)
25 °C 3.3 V 5.0 V 48 kHz 1008 Hz 20 Hz to 20 kHz 2.0 V 0.8 V 4.0 V 1.0 V
DAC Test Conditions Calibrated 0 dB Gain/Attenuation Relative to Full Scale 0 dB Input 10 k Output Load (LINE_OUT) 32 Output Load (HP_OUT) ADC Test Conditions Calibrated 0 dB Gain Input 3.0 dB Relative to Full Scale
Parameter ANALOG INPUT Input Voltage (RMS values assume sine-wave input) LINE_IN, AUX, CD, PHONE_IN MIC_IN with 20 dB gain MIC_IN with 0 dB gain Input Impedance1 Input Capacitance1 MASTER VOLUME Step Size (0 dB to 46.5 dB); LINE_OUT_L, LINE_OUT_R Output Attenuation Range1 Step Size (0 dB to 46.5 dB); MONO_OUT Output Attenuation Range1 Step Size (0 dB to 46.5 dB); HP_OUT_R, HP_OUT_L Output Attenuation Range1 Mute Attenuation of 0 dB Fundamental1 PROGRAMMABLE GAIN AMPLIFIER--ADC Step Size (0 dB to 22.5 dB) PGA Gain Range ANALOG MIXER--INPUT GAIN/AMPLIFIERS/ATTENUATORS Signal-to-Noise Ratio (SNR) CD to LINE_OUT Other to LINE_OUT Step Size (+12 dB to 34.5 dB): (All steps tested) MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC Input Gain/Attenuation Range: MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC DIGITAL DECIMATION AND INTERPOLATION FILTERS Pass Band Pass Band Ripple Transition Band Stop Band Stop Band Rejection Group Delay Group Delay Variation over Pass Band
1
Min
Typ
Max
Unit
1 2.83 0.1 0.283 1 2.83 20 5
7.5
Vrms Vp-p Vrms Vp-p Vrms Vp-p k pF
1.5 46.5 1.5 46.5 1.5 46.5 80 1.5 22.5
dB dB dB dB dB dB dB dB dB
90 90 1.5 46.5 0 0 . 4 × FS 0 . 6 × FS 74 1 6 / FS 0 0 . 4 × FS ± 0.09 0 . 6 × FS
dB dB dB dB Hz dB Hz Hz dB s µs
2
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AD1981A
SPECIFICATIONS
Parameter ANALOG-TO-DIGITAL CONVERTERS Resolution Total Harmonic Distortion (THD) Dynamic Range (60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion (CCIF Method)1 ADC Crosstalk1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) LINE_IN to Other Gain Error2 (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error1 DIGITAL-TO-ANALOG CONVERTERS Resolution Total Harmonic Distortion (THD) LINE_OUT Total Harmonic Distortion (THD) HP_OUT Dynamic Range (60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion (CCIF Method)1 Gain Error (Actual Output Full-Scale Voltage Relative to Nominal Output Full-Scale) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)1 Total Audible Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz)1 ANALOG OUTPUT Full-Scale Output Voltage; LINE_OUT and MONO_OUT Output Impedance1 External Load Impedance1 Output Capacitance1 External Load Capacitance Full-Scale Output Voltage; HP_OUT (0 dB Gain) External Load Capacitance1 External Load Impedance1 V REF VREFOUT (selectable to 3.70 V nominal) VREFOUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output) STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH): Digital Inputs Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 2 mA Low Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current POWER SUPPLY Power Supply Range Analog (AVDD) Power Supply Range Digital (DVDD) Power Dissipation 5 V/3.3 V Analog Supply Current 5 V (AVDD) Digital Supply Current 3.3 V(DVDD) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1 (At Both Analog and Digital Supply Pins, Both ADCs and DACs) CLOCK SPECIFICATIONS Input Clock Frequency Recommended Clock Duty Cycle REV. 0 3
1
Min
Typ 16 84
Max
Unit Bits dB dB dB
80
85 85 80 100 80 ± 10 ± 0.5 ±5
dB dB % dB mV Bits dB dB dB dB
20 85 75 85 90 100 ± 10 ± 0.7 80 40 1 2.83 800 10 15 100 1 100 32 2.05 2.25 2.25 ±5 0.65 × DVDD 0.9 × DVDD 10 10 4.65 3.15 2.45 5
% dB dB dB Vrms Vp-p k pF pF Vrms pF V V mA mV V V V V µA µA V V mW mA mA dB MHz %
0.35 × DVDD 0.1 × DVDD 10 10 5.25 3.45 555 78 50
40 24.576 50
40
60
AD1981ASPECIFICATIONS
Parameter POWER-DOWN STATES (Fully Active) ADC DAC ADC + DAC Mixer ADC + Mixer DAC + Mixer ADC + DAC + Mixer Standby Headphone Standby
3
Set Bits (No Bits Value) PR0 PR1 PR1, PR0 PR2 PR2, PR0 PR2, PR1 PR2, PR1, PR0 PR5, PR4, PR3, PR2, PR1, PR0 PR6
DVDD Typ 47 39 32 13 47 39 32 13 0 47
AVDD Typ 53 47 40 34 21 16 8 1 0 40
Unit mA mA mA mA mA mA mA mA mA mA
Parameter TIMING PARAMETERS (Guaranteed over Operating Temperature Range) RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Start-Up Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Start-Up Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter1 BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to HI-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
NOTES 1 Guaranteed but not tested. 2 Measurement reflects main ADC. 3 Values presented with V REFOUT not loaded. Specifications subject to change without notice.
Symbol
Min
Typ
Max
Unit
tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN t FALLDIN t RISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF
1.0 162.8 1.3 19.5 162.8 12.288 81.4 750 42 38 48.0 20.8 2.5 4 4 4 4 4 4 4 4
ms ns ms ns MHz ns ps ns ns kHz ms ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns
32.56 32.56
48.84 48.84
5 5 2 2 2 2 2 2 2 2 0 15
6 6 6 6 6 6 6 6 1.0
25 15 50 15
4
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AD1981A
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted.)
Power Supplies Digital (DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +3.6 V Analog (AVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6.0 V Input Current (except Supply Pins) . . . . . . . . . . . . . . . ± 10 mA Signals Pins Digital Input Voltage . . . . . . . . . . . . . 0.3 V to DVDD +0.3 V Analog Input Voltage . . . . . . . . . . . . 0.3 V to AVDD +0.3 V Ambient Temperature Range (Operating) . . . . . . . 0°C to 70°C
Ambient Temperature Rating (TQFP Package) TAMB = TCASE ( PD CA ) TCASE = Case Temperature in °C PD = Power Dissipation in W JA Thermal Resistance (Junction-to-Ambient) . . . 76.2°C/W JC Thermal Resistance (Junction-to-Case) . . . . . . . 17°C/W JA Thermal Resistance (Case-to-Ambient) . . . . . 52.2°C/W Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD1981AJST
*ST = Thin Quad Flatpack
Temperature Range 0°C to 70°C
Package Description 48-Lead LQFP
Package Option* ST-48
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1981A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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