|
|
Part: AD1981BJST
Category:
Description: AD1981B ac '97 SoundMAX® Codec
Company: Analog Devices
Datasheet: Download AD1981BJST datasheet File size : 454 kB
Request For quote: Find where to buy AD1981BJST
Datasheet text preview:
a
FEATURES AC '97 2.3 COMPATIBLE FEATURES S/PDIF Output, 20 Bits Data Format, Supporting 48 kHz and 44.1 kHz Sample Rates Integrated Stereo Headphone Amplifier Variable Sample Rate Audio External Audio Power-Down Control Greater than 90 dB Dynamic Range Stereo Full-Duplex Codec 20-Bit PCM DAC 3 Analog Line-Level Stereo Inputs for Line-In, AUX, and CD Mono Line-Level Phone Input Dual MIC Input with Built-In Programmable Preamp High Quality CD Input with Ground Sense
AC '97 SoundMAX Codec AD1981B
Mono Output for Speakerphone or Internal Speaker Power Management Support 48-Lead LQFP Package ENHANCED FEATURES Stereo MIC Preamps Support Built-In Digital Equalizer Function for Optimized Speaker Sound Full-Duplex Variable Sample Rates from 7040 Hz to 48 kHz with 1 Hz Resolution Jack Sense Pins Provide Automatic Output Switching Software Programmed VREFOUT Output for Biasing Microphone and External Power Amp Split Power Supplies: 3.3 V Digital and 5 V Analog Multiple Codec Configuration Options
®
FUNCTIONAL BLOCK DIAGRAM
VREFOUT VREF XTL_OUT XTL_IN SPDIF
AD1981B
G MIC PREAMP MIC1
VOLTAGE REFERENCE
MS
CODEC CORE
G G
SPDIF TX
MIC2 PHONE_IN CD_L CD_GND CD_R AUX_L AUX_R LINE_IN_L LINE_IN_R CD DIFF AMP
2CMIC
PCM L/R ADC RATE
PLL
ID0
RECORD SELECTOR
G
M
16-BIT - ADC 16-BIT - ADC ID1
G
M
G G MONO_OUT M A
M M
16-BIT - ADC 16-BIT - ADC
AC '97 INTERFACE
ADC AND DAC SLOT LOGIC
RESET
SYNC
MIX
BIT_CLK
EQ CORE STORAGE
M
GA
20-BIT - DAC
BYPASS
SDATA_OUT
EQ
HP_OUT_L
HP
M
A
OUTPUT SELECTOR
M GA GA M M M M GA GA GA GA M M M M M GA GA
GA
20-BIT - DAC PCM FRONT DAC RATE
BYPASS
SDATA_IN
EQ
LINE_OUT_L
MZ
A
G = GAIN A = ATTENUATION M = MUTE Z = HIGH Z
LINE_OUT_R
MZ
A
AC '97 CONTROL REGISTERS
HP_OUT_R
HP
M
A M
ANALOG MIXING CONTROL LOGIC
EAPD
JS0
JS1
EAPD
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD1981BSPECIFICATIONS
STANDARD TEST CONDITIONS, UNLESS OTHERWISE NOTED DAC Test Conditions
Temperature Digital Supply (VDD) Analog Supply (VCC) Sample Rate (FS) Input Signal Analog Output Pass Band
25 °C 3.3 V 5.0 V 48 kHz 1008 Hz 20 Hz to 20 kHz
Calibrated 3 dB Attenuation Relative to Full Scale 0 dB Input 10 k Output Load (LINE_OUT) 32 Output Load (HP_OUT)
ADC Test Conditions
Calibrated 0 dB Gain Input 3.0 dB Relative to Full Scale
Parameter ANALOG INPUT Input Voltage (rms Values Assume Sine Wave Input) LINE_IN, AUX, CD, PHONE_IN MIC_IN with +20 dB Gain MIC_IN with 0 dB Gain Input Impedance1 Input Capacitance1 MASTER VOLUME Step Size (0 dB to 46.5 dB): LINE_OUT_L, LINE_OUT_R Output Attenuation Range1 Step Size (0 dB to 46.5 dB): MONO_OUT Output Attenuation Range1 Step Size (0 dB to 46.5 dB): HP_OUT_R, HP_OUT_L Output Attenuation Range Span1 Mute Attenuation of 0 dB Fundamental1 PROGRAMMABLE GAIN AMPLIFIER--ADC Step Size (0 dB to 22.5 dB) PGA Gain Range ANALOG MIXER--INPUT GAIN/AMPLIFIERS/ATTENUATORS Signal-to-Noise Ratio (SNR) CD to LINE_OUT Other to LINE_OUT1 Step Size (+12 dB to 34.5 dB) (All Steps Tested): MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC Input Gain/Attenuation Range: MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC DIGITAL DECIMATION AND INTERPOLATION FILTERS Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Rejection Group Delay Group Delay Variation over Pass Band
1
Min
Typ
Max
Unit
1 2.83 0.1 0.283 1 2.83 20 5 1.5 46.5 1.5 46.5 1.5 46.5 80 1.5 22.5
7.5
V rms V p-p V rms V p-p V rms V p-p k pF dB dB dB dB dB dB dB dB dB
90 90 1.5 46.5 0 0.4 0.6 74 fS fS 16/fS 0 0.4 f S ± 0.09 0.6 f S
dB dB dB dB Hz dB Hz Hz dB sec µs
2
REV. A
AD1981B
Parameter ANALOG-TO-DIGITAL CONVERTERS Resolution Total Harmonic Distortion (THD) Dynamic Range (60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion1 (CCIF Method) ADC Crosstalk1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line_In to Other Gain Error2 (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error1 DIGITAL-TO-ANALOG CONVERTERS Resolution Total Harmonic Distortion (THD) LINE_OUT Total Harmonic Distortion (THD) HP_OUT Dynamic Range (60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion1 (CCIF Method) Gain Error2 (Output FS Voltage Relative to Nominal Output FS Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk1 (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) Total Audible Out-of-Band Energy1 (Measured from 0.6 fS to 20 kHz) ANALOG OUTPUT Full-Scale Output Voltage; LINE_OUT and MONO_OUT Output Impedance1 External Load Impedance1 Output Capacitance1 External Load Capacitance1 Full-Scale Output Voltage; HP_OUT (0 dB Gain) External Load Impedance1 V REF VREF_OUT (Programmable to 3.70 V Nominal) VREF_OUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output) STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH): Digital Inputs Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 2 mA Low Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current POWER SUPPLY Power Supply Range--Analog (AVDD) Power Supply Range--Digital (DVDD) Power Dissipation--5 V/3.3 V Analog Supply Current--5 V (AVDD) Digital Supply Current--3.3 V (DVDD) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1 (At Both Analog and Digital Supply Pins, Both ADCs and DACs) Min Typ 16 84 85 85 80 100 Max Unit Bits dB dB dB dB dB % dB mV Bits dB dB dB dB % dB dB dB V rms V p-p k pF pF V rms V V mA mV V V V V µA µA V V mW mA mA dB
80
80 ± 10 ± 0.5 ±5
85
20 85 75 90 100 ± 10
± 0.7 80
40 1 2.83 800 10 15 100 1 32 2.05 2.25 2.25 ±5 0.65 0.9 10 10 4.5 3.0 400 50 46 40 DVDD 0.35 DVDD 0.1 DVDD +10 +10 5.5 3.47 DVDD 2.45 5
REV. A
3
AD1981B
Parameter CLOCK SPECIFICATIONS Input Clock Frequency Recommended Clock Duty Cycle
NOTES 1 Guaranteed but not tested. 2 Measurements reflect main ADC. Specifications subject to change without notice.
1
Min
Typ 24.576 50
Max
Unit MHz %
40
60
Parameter POWER-DOWN STATES* (Fully Active) ADC DAC ADC + DAC Mixer ADC + Mixer DAC + Mixer ADC + DAC + Mixer Standby Headphone Standby
*Values presented with V REFOUT not loaded. Specifications subject to change without notice.
Set Bits (No Bits Value) PR0 PR1 PR1, PR0 PR2 PR2, PR0 PR2, PR1 PR2, PR1, PR0 PR5, PR4, PR3, PR2, PR1, PR0 PR6
DVDD Typ 42 36 29 12 42 36 29 12 0 42
AVDD Typ 51 45 35 28 24 18 9 1.5 0 44
Unit mA mA mA mA mA mA mA mA mA mA
TIMING PARAMETERS
Parameter
(Guaranteed over Operating Temperature Range) Symbol
tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tH O L D tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN t FALLDIN t RISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF
Min 162.8
Typ 1.0 1.3 19.5
Max
Unit ms ns ms ns MHz ppm ns ps ns ns kHz ms ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns
RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Start-Up Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Start-Up Delay BIT_CLK Frequency BIT_CLK Frequency Accuracy BIT_CLK Period BIT_CLK Output Jitter1, 2, 3 BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to HI-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
162.8 12.288 81.4 750 42 38 48.0 20.8 2.5 4 4 4 4 4 4 4 4 ±1 2000 48.84
32.56 32.56 5 5 2 2 2 2 2 2 2 2 0 15
6 6 6 6 6 6 6 6 1.0 25 15 50 15
NOTES 1 Guaranteed but not tested. 2 Output jitter is directly dependent on crystal input jitter. 3 Maximum jitter specification for noncrystal operation only. Crystal operation maximum is much lower. Specifications subject to change without notice.
4
REV. A
AD1981B
tRST2CLK tRST_LOW
RESET
tTRI2ACTV
BIT_CLK
tTRI2ACTV
SDATA_IN
Figure 1. Cold Reset Timing (Codec is Supplying the Bit_CLK Signal)
tSYNC_HIGH
SYNC
tSYNC2CLK
BIT_CLK
Figure 2. Warm Reset Timing
tCLK_LOW
BIT_CLK
tCLK_HIGH tCLK_PERIOD tSYNC_LOW
SYNC
tSYNC_HIGH tSYNC_PERIOD
Figure 3. Clock Timing
BIT_CLK
tRISECLK
tFALLCLK
SYNC
tRISESYNC
tFALLSYNC
SDATA_IN
tRISEDIN
tFALLDIN
SDATA_OUT
tRISEDOUT
tFALLDOUT
Figure 4. Signal Rise and Fall Times
REV. A
5
Others parts begin by ad
AD-1 AD-2 AD-3 AD-4 AD-5 AD-6 AD-7 AD-8 AD-9 AD-10 AD-11 AD-12 AD-13 AD-14 AD-15 AD-16 AD-17 AD-18 AD-19 AD-20 AD-21 AD-22 AD-23 AD-24 AD-25 AD-26 AD-27 AD-28 AD-29 AD-30 AD-31 AD-32 AD-33 AD-34 AD-35 AD-36 AD-37 AD-38 AD-39 AD-40 AD-41 AD-42 AD-43 AD-44 AD-45 AD-46 AD-47 AD-48 AD-49 AD-50 AD-51 AD-52 AD-53 AD-54 AD-55 AD-56 AD-57 AD-58 AD-59 AD-60 AD-61 AD-62 AD-63 AD-64 AD-65 AD-66 AD-67 AD-68 AD-69 AD-70 AD-71 AD-72 AD-73 AD-74 AD-75 AD-76 AD-77 AD-78 AD-79 AD-80 AD-81 AD-82 AD-83 AD-84 AD-85 AD-86 AD-87 AD-88 AD-89 AD-90 AD-91 AD-92 AD-93 AD-94 AD-95 AD-96 AD-97 AD-98 AD-99 AD-100 AD-101 AD-102 AD-103 AD-104 AD-105 AD-106 AD-107
|
|
|
