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Details, datasheet, quote on part number:AD1991
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| Part: | AD1991 |
| Category: | Multimedia => Audio => Amplifiers => Power Amplifiers |
| Description: | Class D/1-Bit Audio Power Amplifier Output Stage |
| Company: | Analog Devices |
| Datasheet: | Download AD1991 datasheet File size : 206 kB |
| Request For quote: | Find where to buy AD1991
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Datasheet text preview:
Class D/1-Bit Audio Power Output Stage AD1991
FEATURES Class D/1-Bit Audio Power Output Stage 5 V Analog and Digital Supply Voltages Power Stage Power Supply 8 V to 20 V Output Power @ 0.1% THD + N Stereo Mode 2 20 W @ 4 @ 14.4 V 2 20 W @ 8 @ 20 V Mono Mode 1 40 W @ 4 @ 20 V RON 85% @ Full Power/8 E lickless Mute Function Turn-On and Turn-Off Pop Suppression Short-Circuit Protection Overtemperature Protection Data Loss Protection 2-Channel BTL Outputs or 4-Channel Single-Ended Outputs 52-Lead Exposed Pad TQFP Package Low Cost DMOS Process APPLICATIONS PC Audio Systems Minicomponents Automotive Amplifiers Home Theater Systems Televisions GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS 2-Channel Mode
AVDD DVDD PVDD 6 OUTA INA LEFT INPUT A1 A2 3
INB
B1 B2
LEVEL SHIFTER AND SWITCH CONTROL H-BRIDGE
OUTB 3 OUTC
INC RIGHT INPUT
C1 C2
3
IND
D1 OUTD D2 3 CURRENT OVERLOAD THERMAL SHUTDOWN THERMAL WARNING DATA LOSS 14 PGND
CLK RST/PDN MUTE
n THERMAL PROTECTION SHORT-CIRCUIT PROTECTION MUTE CONTROL
4 AGND DGND
2 TEST CONTROL
4-Channel Mode
AVDD DVDD PVDD 6
The AD1991 is a 2-channel BTL or 4-channel single-ended class D audio power output stage. The part is configured during reset to be in either 2-channel mode or 4-channel mode. To protect the IC as well as the connected speakers, the AD1991 provides turn-on and turn-off pop suppression, short-circuit protection, and overtemperature shutdown. To control the IC, a power-down/reset input and a mute pin are available. The output stage can be operated over a power supply range from 8 V to 20 V. In 2-channel mode, Transistors A1, B2, C1, and D2 are turned on by a Logic 1 on inputs INA and INC, and Transistors A2, B1, C2, and D1 are turned on by a Logic 0 on inputs INA and INC. In 4-channel mode, Transistors A1, B1, C1, and D1 are turned on by a Logic 1 on the four inputs, and Transistors A2, B2, C2, and D2 are turned on by a Logic 0 on the four inputs (see the Functional Block Diagrams).
INA
A1 A2
OUTA 3
LOAD REQUIRING DC VOLTAGE SUPPLY
INB
B1 B2
LEVEL SHIFTER AND SWITCH CONTROL H-BRIDGE
OUTB 3
INC
C1 C2
OUTC 3
IND
D1 D2
OUTD 3
LOAD REQUIRING DC VOLTAGE SUPPLY
CLK RST/PDN MUTE
n THERMAL PROTECTION SHORT-CIRCUIT PROTECTION MUTE CONTROL
CURRENT OVERLOAD THERMAL SHUTDOWN THERMAL WARNING DATA LOSS 14
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
4 AGND DGND
2 TEST CONTROL
PGND
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
= 5 V, DV = 20 V, Ambient Temperature = 25 C, unless AD1991SPECIFICATIONS1 L(AoVad Impedance = 85 V, ,PV = otherwise noted.)
DD DD DDX
Parameter OUTPUT POWER PO (f = 1 kHz SINE WAVE) EFFICIENCY R ON Per High-Side Transistor Per Low-Side Transistor Temperature Coefficient THERMAL WARNING ACTIVE THERMAL SHUTDOWN ACTIVE OVERCURRENT SHUTDOWN ACTIVE POWER SUPPLIES Supply Voltage AVDD Supply Voltage DVDD Supply Voltage PVDDX Power-Down Current A V DD D VDD P VDDX Operating Current A V DD D VDD P VDDX DIGITAL I/O Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Leakage Current on Digital Inputs
NOTES 1 Performance of both channels is identical. 2 Measurement requires PWM modulator. Specifications subject to change without notice.
2
Min
Typ 20 20 87 260 190 0.7 135 150 5 5.0 5.0 8 to 20 6 1 17 1.8 4 40
Max
Unit W W %
Test Conditions RL = 4 , PVDDX = 14 V RL = 8 , PVDDX = 20 V f = 1 kHz, PO = 20 W, RL = 8 @1A @1A Die temperature Die temperature
320 235
3.8 4.5 4.5 6.5
6.75 5.5 5.5 22.5 14 13
m m m /°C °C °C A V V V µA µA µA mA mA mA
RST/PDN held low RST/PDN held low RST/PDN held low
2.75 5.2
50:50 384 kHz square wave on INA and INC
2.0 DVDD 0.8
D VD D 1.2 0.4 10
V V V V µA
@ 2 mA @ 2 mA
DIGITAL TIMING CHARACTERISTICS
Symbol tPDL tPST tNOL tPDRP tMSU tMH tMPDL Parameter
(Guaranteed over 40 C to +85 C, AVDD = DVDD = 5 V Edge Speed = Slowest, Nonoverlap Time = Shortest.)
Min Typ 3.5 25 to 40 20 5 5
10%, PVDDX = 20 V
Max 30
10%,
Unit ns ns ns ns ns ns s
Input transition to output initial response Power transistor switching time Nonoverlap time RST/PDN minimum low pulsewidth Mode pin setup time before RST/PDN going high Mode pin hold time after RST/PDN going high MUTE asserted to output initial response
3
Specifications subject to change without notice.
2
REV. 0
AD1991
INA
tPST tPST
tPST tPST
tNOL tPDL tPDL
tNOL
OUTA OUTB
Figure 1. Output Timing
RST/PDN
tPDRP
MODEx
tMSU
tMH
Figure 2. RESET and Mode Timing
MUTE
tPST
tPST
OUTx
tMPDL
tMPDL
Figure 3. MUTE Timing
REV. 0
3
AD1991
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C, unless otherwise noted.)
AVDD, DVDD to AGND, DGND . . . . . . . . . . 0.3 V to +6.5 V PVDDX to PGNDx2 . . . . . . . . . . . . . . . . . . . 0.3 V to +30.0 V AGND to DGND to PGNDx . . . . . . . . . . . . 0.3 V to +0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +0.5 V Operating Temperature Range (Ambient) Industrial . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to +85°C Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C JC Thermal Resistance3 . . . . . . . . . . . . . . . . . . . . . . . 1°C/W Lead Temperature Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Including any induced voltage due to inductive load. 3 With respect to the temperature of the exposed pad.
ORDERING GUIDE
Model AD1991ASV AD1991ASVRL EVAL-AD1991EB
Temperature Range 40°C to +85°C 40°C to +85°C
Package Description Thin Quad Flat Pack [TQFP] Thin Quad Flat Pack [TQFP] Evaluation Board
Package Option SV-52 SV-52
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1991 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
4
REV. 0
AD1991
PIN CONFIGURATION
MODE1 AVDD MODE0 AGND PGND1 PGND1 PGND1 AGND PGND2 PGND2 PGND2
39 PGND2 38 OUTC 37 OUTC 36 OUTC 35 PVDD2 34 PVDD2 33 PVDD2 32 OUTD 31 OUTD 30 OUTD 29 PGND2 28 PGND2 27 PGND2 14 15 16 17 18 19 20 21 22 23 24 25 26
AGND
52 51 50 49 48 47 46 45 44 43 42 41 40
PGND1
1
OUTA 2 OUTA 3 OUTA PVDD1 PVDD1 PVDD1
4 5 6 7
PIN 1 IDENTIFIER
AD1991
TOP VIEW (Not to Scale)
OUTB 8 OUTB 9 OUTB 10 PGND1 11 PGND1 12 PGND1 13
DGND
INB DVDD
AGND
MUTE INC
ERR0 INA
IND
PIN FUNCTION DESCRIPTIONS
Pin No.
1 2, 3, 4 5, 6, 7 8, 9, 10 11, 12, 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27, 28, 29 30, 31, 32 33, 34, 35 36, 37, 38 39, 40, 41, 42 43, 45, 48, 49 44 46 47 50, 51, 52
Mnemonic In/Out
PGND1 OUTA P V DD1 OUTB PGND1 ERR3 ERR2 ERR1 ERR0 INA INB D V DD DGND MUTE INC IND R S T /P D N CLK PGND2 OUTD PV DD2 OUTC PGND2 AGND MODE0 A V DD MODE1 PGND1 O O I/O I/O I/O I/O I I
Description
Negative power supply for high power Transistors A2 and B2. Output of transistor pair A1 and A2. Positive power supply for high power Transistors A1 and B1. Output of transistor pair B1 and B2. Negative power supply for high power Transistors A2 and B2. Edge speed setting MSB during RESET/active low thermal shutdown error output during normal operation. Edge speed setting Bit 1 during RESET/active low thermal warning error output during normal operation. Nonoverlap time setting MSB during RESET/active thermal low shutdown error output during normal operation. Nonoverlap time setting Bit 1 during RESET/active low data-loss error output or low-side transistor disable input during normal operation. Control pin for Transistors A1 and A2 always; also control pin for B1 and B2 in 2-channel mode. Edge speed setting LSB during RESET/during normal operation, control pin for Transistors B1 and B2 in 4-channel mode; no function in 2-channel mode. Positive power supply for low power digital circuitry. Negative power supply for low power digital circuitry. Active low clickless mute input. Control pin for Transistors C1 and C2 always; also control pin for D1 and D2 in 2-channel mode. Nonoverlap time setting LSB during RESET/during normal operation, control pin for Transistors D1 and D2 in 4-channel mode; no function in 2-channel mode. Active low RESET/power-down input. External clock input in external clock mode. Negative power supply for high power Transistors C2 and D2. Output of transistor pair D1 and D2. Positive power supply for high power Transistors C1 and D1. Output of transistor pair C1 and C2. Negative power supply for high power Transistors C2 and D2. Negative power supply for low power analog circuitry. Clock source select (referenced to AGND); normally connected to AGND. Positive power supply for low power analog circuitry. Channel mode select (referenced to AGND). Negative power supply for high power Transistors A2 and B2.
I I I I I O O
I
REV. 0
5
RST/PDN CLK
ERR3 ERR2
ERR1
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