|
Details, datasheet, quote on part number:AD28MSP01KST
| |
Datasheet text preview:
a
FEATURES Complete Analog l/O Port for DSP-Based FAX/MODEM Applications Linear-Coded 16-Bit Sigma-Delta ADC Linear-Coded 16-Bit Sigma-Delta DAC On-Chip Anti-Alias and Anti-lmage Filters Digital Resampling/lnterpolation Filter 7.2 kHz, 8.0 kHz, and 9.6 kHz Sampling Rates 8/7 Mode for 8.23 kHz, 9.14 kHz, and 10.97 kHz Sampling Rates Synchronous and Asynchronous DAC/ADC Modes Bit and Baud Clock Generation Transmit Digital Phase-Locked Loop for Terminal Synchronization Independent Transmit and Receive Phase Adjustment Serial Interface to DSP Processors +5 V Operation with Power-Down Mode 28-Pin Plastic DlP/44-Lead PLCC/28-Lead SOIC APPLICATIONS High Performance DSP-Based Modems V.32ter, V.32bis, V.32, V.22bis, V.22, V.21, Bell 212A, 103 Fax and Cellular-Compatible Modems V.33, V.29, V.27ter, V.27bis, V.27, V.26bis Integrated Fax, Modem, and Speech Processing GENERAL DESCRIPTION
ANALOG INPUTS
PSTN Signal Port AD28msp01
FUNCTIONAL BLOCK DIAGRAM
16-BIT SIGMA-DELTA ADC DIGITAL DATA AND CONTROL SERIAL PORT
VOLTAGE REFERENCE
RESAMPLING INTERPOLATION FILTER
DIFFERENTIAL ANALOG OUTPUT
16-BIT SIGMA-DELTA DAC
CLOCK INPUTS CLOCK OUTPUTS
CLOCK GENERATION
The AD28msp01 is a complete analog front end for high performance DSP-based modems. The device includes all data conversion, filtering, and clock generation circuitry needed to implement an echo-cancelling modem with a single host digital signal processor. Software-programmable sample rates and clocking modes support all established modem standards. The AD28msp01 simplifies overall system design by requiring only +5 volts. The inclusion of on-chip anti-aliasing and anti-imaging filters and 16-bit sigma-delta ADC and DAC ensures a highly integrated and compact solution for FAX or data MODEM applications. Sigma-delta conversion technology eliminates the need for complex off-chip anti-aliasing filters and sample-and-hold circuitry. The AD28msp01 utilizes advanced sigma-delta technology to move the entire echo-cancelling modem implementation into the digital domain. The device maintains a 72 dB SNR throughout all filtering and data conversion. Purely DSP-based echo cancellation algorithms can thereby maintain robust bit error rates under worst-case signal attenuation and echo amplitude conditions. The AD28msp01's on-chip interpolation filter resamples the received signal after echo cancellation in the DSP, freeing the processor for other voice or data communications tasks. REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
On-chip bit and baud clock generation circuitry provides for either synchronous or asynchronous operation of the transmit (DAC) and receive (ADC) paths. Each path features independent phase advance and retard adjustments via software control. The AD28msp01 can also synchronize modem operation to an external terminal bit clock. The AD28msp01's serial I/O port provides an easy interface to host DSP microprocessors such as the ADSP-2101, ADSP-2105, and ADSP-2111. Packaged in a 28-pin plastic DIP, 44-lead PLCC, 44-pin TQFP, or 28-lead SOIC, the AD28msp01 provides a compact solution for space-constrained environments. The device operates from a +5 V supply and offers a low power sleep mode for battery-powered systems. A detailed block diagram of the AD28msp01 is shown in Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD28msp01
16-BIT SIGMA-DELTA ADC
VFB SDOFS VI N INPUT AMP ANALOG SIGMA-DELTA MODULATOR 1 DIGITA L DECIMATION FILTER 16 DIGITAL ANTI-ALIASING LOW-PASS FILTER 16 DIGITAL HIGH -PASS FILTER 16 SDO
1.728 MHz
28.8/32.0/38.4 kHz
7.2/8.0/9.6 kHz
7.2/8.0/9.6 kHz
500k
VOLTAGE REFERENCE
RESAMPLING INTERPOLATION FILTER
SCLK SERIAL PORT
16-BIT SIGMA-DELTA DAC
VO U T + VO U T OUTPUT DIFF. AMP ANALOG SMOOTHING FILTER 1 D IGITAL SIGMA-DELTA MOD ULATOR 16 DIGITAL INTERPOLA TION FILTER 16 DIGITAL ANTI-IMAGING LOW-PASS FILTER 16 SDI
SDIFS 1.728 MHz INTERNAL CLOCK 1.728 MHz 28.8/32.0/38.4 kHz 7.2/8.0/9.6 kHz
TSYNC
CLOCK GENERATION
CONTROL CIRCUITRY A ND SEQUENCER
CONTROL REGISTERS
tC ON V tB A U D
tB IT
rCO NV rBAUD
rBIT
MC L K
RESET
CS
Figure 1. AD28msp01 Block Diagram
PIN DESCRIPTIONS
Name
Type Description
Name SDOFS
Type Description O/Z Framing synchronization signal for serial data transfers from the AD28msp01 (via the SDO pin). This pin is 3-stated when CS is low.
Analog Interface V IN I Analog input to the inverting terminal of the input amplifier. V FB O Feedback terminal of the input amplifier. V OUTP O Analog output from the noninverting terminal of the output differential amplifier. V OUTN O Analog output from inverting terminal of the output differential amplifier. Serial Interface SCLK O/Z Serial clock used for clocking data or control bits to/from the serial port (SPORT). The frequency of this clock is 1.7280 MHz. This pin is 3-stated when the CS is low. SDI I Serial data input of the SPORT. Both data and control information are input on this pin. This pin is ignored when CS is low. SDO O/Z Serial data output of the SPORT. Both data and control information are output on this pin. This pin is 3-stated when CS is low. SDIFS I Framing synchronization signal for serial data transfers to the AD28msp01 (via the SDI pin). This pin is ignored when CS is low.
Clock Generation TSYNC I Transmit synchronization clock. This signal is used to synchronize the transmit clocks and the converter clocks to an external terminal/ bit-rate clock. It is used in the V.32 TSYNC and Asynchronous TSYNC modes and is ignored in other operating modes. The frequency of the external clock must be programmed in Control Register 0. This pin must be tied high or low if it is not being used. TBIT O Transmit bit rate clock. This is an output clock whose frequency is programmable via Control Register 3. It is synchronized with the TCONV clock. TBAUD O Transmit baud rate clock. This is an output clock whose frequency is programmable via Control Register 3. It is synchronized with the TCONV clock.
2
REV. A
AD28msp01
PIN DESCRIPTIONS (Continued) FUNCTIONAL DESCRIPTION A/D Conversion
Name
Type Description Transmit conversion clock. This clock indicates when the ADC has finished a sampling cycle. The frequency of TCONV is programmed by setting the sample rate field in Control Register 0. The programmed TCONV rate can be scaled by a factor of 8/7 by setting Bit 9 in Control Register 1. The phase of TCONV can be adjusted by writing the Transmit Phase Adjust Register (Control Register 5). Receive bit rate clock. This is an output clock whose frequency is programmable via Control Register 2. It is synchronized with the RCONV clock. Receive baud rate clock. This is an output clock whose frequency is programmable via Control Register 2. It is synchronized with the RCONV clock. Receive conversion clock. This clock indicates when the DAC has finished a sampling cycle. The frequency of RCONV is programmed by setting the sample rate field in Control Register 0. The programmed RCONV rate can be scaled by a factor of 8/7 by setting Bit 9 in Control Register 1. The phase of RCONV can be adjusted by writing the Receive Phase Adjust Register (Control Register 4).
TCONV O
The A/D conversion circuitry of the AD28msp01 consists of an analog input amplifier and a sigma-delta analog-to-digital converter (ADC). The analog input signal to the AD28msp01 must be ac coupled.
Analog Input Amplifier
The analog input amplifier is internally biased by an on-chip voltage reference in order to allow operation of the AD28msp01 with a +5 V power supply. Input signal level to the sigma-delta modulator should not exceed VINMAX, which is specified under "Analog Interface Electrical Characteristics." Refer to "Analog Input" in the "Design Considerations" section of this data sheet for more information.
ADC
RBIT
O
RBAUD O
RCONV O
The ADC consists of a 3rd-order analog sigma-delta modulator, a decimation filter, an anti-aliasing low-pass filter, and a highpass filter. The analog input is applied to the input amplifier. The output of this amplifier is applied to an analog sigma-delta modulator which noise-shapes it and produces 1-bit samples at a 1.7280 MHz rate. This bit stream is fed to the decimation filter, which increases the resolution to 16-bits and decreases the sampling frequency. The parallel data stream is then processed by the anti-aliasing low-pass filter which further reduces the sampling rate. Finally, the high-pass filter removes input frequency components at the low end of the spectrum. Either the high-pass filter alone or the high-pass/anti-aliasing low-pass filter combination can be bypassed by setting the appropriate bits in Control Register 1, thus producing samples at 7.2/8.0/9.6 kHz or 28.8/32.0/38.4 kHz, respectively. The gain and the frequency response of the AD28msp01 are altered when these filters are bypassed. The DSP processor that receives samples from the AD28msp01 may need to compensate for this change.
Decimation Filter
Miscellaneous MCLK I AD28msp01 master clock input. The frequency of this clock must be 13.824 MHz to guarantee listed specifications. RESET I Active-low chip reset. This signal sets all AD28msp01 control registers to their default values and clears the device's digital filters. SPORT output pins are 3-stated when RESET is low. SPORT input pins are ignored when RESET is low. CS I Active-high chip select. This signal 3-states all SPORT output pins and forces the AD28msp01 to ignore all SPORT input pins. If CS is deasserted during a serial data transfer, the 16-bit word being transmitted is lost. Power Supplies V CC Analog supply voltage (nominally +5 V) GNDA Analog ground V DD Digital supply voltage (nominally +5 V) GND D Digital ground
The decimation filter is a sinc4 digital filter that increases resolution to 16 bits and reduces the sample rate to 28.8, 32.0, or 38.4 kHz (depending on the input sample rate). The 16 bit, parallel data stream output of the decimation filter is then processed by the anti-aliasing low-pass filter.
Anti-Aliasing Low-Pass Filter
The anti-aliasing low-pass filter further reduces the sampling rate by a factor of four to 7.2 kHz, 8.0 kHz, or 9.6 kHz (depending on the output sample rate of the decimation filter). The output is fed to the high-pass filter. The low-pass/high-pass filter combination can be bypassed by setting the appropriate bits in Control Register 1. If the filters are bypassed, the signal must be scaled by the following multipliers to achieve normal levels: 2.046 for 9.6 kHz, 0.987 for 8.0 kHz, and 0.647 for 7.2 kHz. When the filters are bypassed, the host DSP must be able to receive data at the 28.8/32.0/38.4 kHz rates. In this case, resampling interpolation should be disabled because of insufficient bandwidth to transmit both ADC and resampled data to the SPORT.
High-Pass Filter
The digital high-pass filter removes frequency components at the low end of the spectrum. The high pass filter can be bypassed by setting the appropriate bits in Control Register 1.
REV. A
3
AD28msp01
The output of the ADC is transferred to the AD28msp01's serial port (SPORT) for transmission to the host DSP processor.
D/A CONVERSION
amplifier. Refer to "Analog Output" in the "Design Considerations" section of this data sheet for more information. The VOUTP and VOUTN outputs must be used as differential outputs; do not use either as a single-ended output.
SERIAL PORT
The D/A conversion circuitry of the AD28msp01 consists of a sigma-delta digital-to-analog converter (DAC) and a differential output amplifier.
DAC
The DAC consists of an anti-imaging low-pass filter, an interpolation filter, a digital sigma-delta modulator, and an analog smoothing filter. These filters have the same characteristics as the ADC's anti-aliasing filter and decimation filter. The DAC receives 16-bit samples from the host DSP processor via AD28msp01's SPORT. If the host processor fails to write a new value to the serial port, the existing (previous) data is read again. The data stream is filtered first by the DAC's antiimaging low-pass filter and then by the interpolation filter. The output of the interpolation filter is fed to the DAC's digital sigma-delta modulator, which converts the 16-bit data to 1-bit samples. The output of the sigma-delta modulator is fed to the AD28msp01's analog smoothing filter where it is converted into a low-pass filtered, analog voltage.
Anti-lmaging Low-Pass Filter
The AD28msp01 includes a full-duplex synchronous serial port (SPORT) used to communicate with a host processor. The SPORT is used to read and write all data and control registers in the AD28msp01. The SPORT transfers 16-bit words, MSB first, at a serial clock rate of 1.7280 MHz. When the AD28msp01 exits reset, both the analog circuitry and the digital circuitry are powered down. The serial port will not transmit data to the host until the host sets the digital powerdown bit (PWDD) to 1 in Control Register 1. All control registers should be initialized before this bit is set. The SPORT is configured for an externally generated receive frame sync (SDIFS), an internally generated serial clock (SCLK), and an internally generated transmit frame sync (SDOFS). The host processor should be configured for an external serial clock and receive frame sync and an internal transmit frame sync.
DSP Processor Interface
The anti-imaging low-pass filter filters the 7.2 kHz, 8.0 kHz, or 9.6 kHz data stream form the SPORTs, and raises the sampling rate to 28.8 kHz, 32.0 kHz, or 38.4 kHz. The anti-imaging low-pass filter can be bypassed by setting the appropriate bit in Control Register 1. This results in a gain change. If the filter is bypassed, the signal must be scaled by the following multipliers to achieve normal levels: 2.046 for 9.6 kHz, 0.987 for 8.0 kHz, and 0.647 for 7.2 kHz. When the filter is bypassed, the host DSP must be able to transmit data at the 28.8/32.0/38.4 kHz rates. In this case, resampling interpolation should be disabled because of insufficient bandwidth to transmit both ADC and resampled data to the SPORT.
Interpolation Filter
The AD28msp01-to-host processor interface is shown in Figure 2.
AD28msp01
SDO SDOFS SCLK CS SDI SDIFS
DSP PROCESSOR
SERIAL DATA RECEIVE RECEIVE FRAME SYNC SERIAL CLOCK FLAG SERIAL DATA TRANSMIT TRANSMIT FRAME SYNC
Figure 2. AD28msp01-to-DSP Processor Interface
The AD28msp01's chip select (CS) must be held high to enable SPORT operation. CS can be used to 3-state the SPORT pins and disable communication with the host processor. To use the ADSP-2101 or ADSP-2111 as host DSP processor for the AD28msp01, refer to Figure 3. Note that the ADSP-2101's SPORT0 communicates with the AD28msp01's SPORT while the ADSP-2101's Flag Output (FO) is used to signal the AD28msp01's CS input. SPORT1 on the ADSP-2101 must be configured for flags and interrupts in this system.
AD28msp01
SDO SDOFS SCLK CS SDI SDIFS DR0 RFS0 SCLK0 FO DT0 TFS0
The interpolation filter contains is a sinc4 digital filter which raises the sampling rate to 1.7280 MHz by interpolating between the samples. These 16-bit samples are then processed by the digital sigma-delta modulator which noise-shapes the data stream and reduces the sample width to a single bit stream.
Analog Smoothing Filter
The AD28msp01's analog smoothing filter consists of a 2ndorder Sallen-Key continuous-time filter and a 3rd-order switched capacitor filter. The Sallen-Key filter has a 3 dB point at approximately 80 kHz. The analog smoothing filter converts the 1.7280 MHz bit stream output of the sigma-delta modulator into a low-pass filtered, differential analog signal.
Differential Output Amplifier
ADSP-2101
The differential output amplifier produces the AD28msp01's analog output (VOUTP, VOUTN). It can drive loads of 2 k or greater and has a maximum differential output voltage swing of 6.312 V peak-to-peak. The output signal is dc biased to the AD28msp01's on-chip voltage reference (2.5 V nominal) and can be ac coupled directly to a load or dc coupled to an external
Figure 3. AD28msp01-to-ADSP-2101 Interface
Figure 4 shows an ADSP-2101 assembly language program that initializes the AD28msp01 and implements a digital loopback through the processor.
4
REV. A
AD28msp01
{This ADSP-2101 program initializes the AD28msp01} {and executes a loopback, or talk-through, routine.} . MODULE/RAM/BOOT = 0 MSP01; . VAR/DM/CIRC rec[2]; . VAR/DM/CIRC trans[2]; rset: irq2v: sprt0t: sprt0r: sprt1t: sprt1r: timerv: start: I2 = ^re c ; L2 = %rec; I3 = ^trans; L3 = %trans; M0 = 0; M1 = 1; S1 = 0; DM(0x3000) = SI; init dsp: AX0 = 0x2a0f; DM(0x3ff6) = AX0; AX0 = 0x101f; DM(0x3fff) = AX0; init msp01: IMASK = 0x10; AR = 0; CNTR = 6; DO initi UNTIL CE; TX0 = AR; IDLE; TX0 = SI; IDLE; AY0 = AR; AR = AY0 +1; AX1 = 1; AR = 0x18; TX0 = AX1; IDLE; TX0 = AR; AR = B#0025; DM(0x3ff3) = AR; IMASK = 0x18; JUMP wait; {Ext RFS, Int TfS, Ext SCLK, SLEN = 15} {SPORT0 control register} {Enable SPORT0} {System control register} {Initialize AD28msp01 control register} {Note: This section could be autobuffered.} {Enable SPORT0 TX interrupt} JUMP start; RTI; RTI; RTI; RTI; RTI; RTI; RTI; AX0 = 0x25; DM(0x3ff3) = AX0; RTI; RTI; JUMP receive; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; {Initialize DAGs} {Receive word buffer} {Transmit word buffer} {lnterrupt Vectors}
{Disable TX autobuffer}
{Reset the AD28msp01} {Initialize the ADSP-2101}
{Transmit address} {Transmit control word}
initi:
{Increment address} {Power up AD28msp01}
wait: receive:
{Enable RX autobuffering with I2, M1} {Autobuffer control register} {Enable RX and TX interrupt} {Wait for receive interrupt} {Receive Interrupt Routine}
DM(0x3ff3) = SI; AX1= DM(I2, M1); REV. A 5
{Disable autobuffering} {Read first receive word from buffer}
|
|
