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Details, datasheet, quote on part number:AD28MSP02BR
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Datasheet text preview:
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FEATURES Complete Analog I/O Port for Voiceband DSP Applications Linear-Coded 16-Bit Sigma-Delta ADC Linear-Coded 16-Bit Sigma-Delta DAC On-Chip Anti-Aliasing and Anti-lmaging Filters On-Chip Voltage Reference 8 kHz Sampling Frequency Twos Complement Coding 65 dB SNR + THD Programmable Gain on DAC and ADC Serial Interface To DSP Processors 24-Pin DlP/28-Lead SOIC Single 5 V Power Supply
VOICEBAND ANALOG INPUT A MUX VOICEBAND ANALOG INPUT B
Voiceband Signal Port AD28msp02
FUNCTIONAL BLOCK DIAGRAM
16-BIT SIGMADELTA ADC DIGITAL DATA AND CONTROL VOLTAGE REFERENCE SERIAL PORT
+20dB AMP
DIFFERENTIAL ANALOG OUTPUT
PGA
16-BIT SIGMADELTA DAC
GENERAL DESCRIPTION
Analog Input Amplifiers
The AD28msp02 Voiceband Signal Port is a complete analog front end for high performance voiceband DSP applications. Compared to traditional µ-law and A-law codecs, the AD28msp02's linear-coded ADC and DAC maintain wide dynamic range while maintaining superior SNR and THD. A sampling rate of 8.0 kHz coupled with 65 dB SNR + THD performance make the AD28msp02 attractive in many telecom and speech processing applications, for example digital cellular radio and high quality telephones. The AD28msp02 simplifies overall system design by requiring only a single +5 V power supply. The inclusion of on-chip anti-aliasing and anti-imaging filters, 16-bit sigma-delta ADC and DAC, and programmable gain amplifiers ensures a highly integrated and compact solution to voiceband analog processing requirements. Sigma-delta conversion technology eliminates the need for complex off-chip antialiasing filters and sample-and-hold circuitry. The AD28msp02's serial I/O port provides an easy interface to host DSP microprocessors such as the ADSP-2101, ADSP-2105 and ADSP-2111. The AD28msp02 is available in a 24-pin, 0.3" plastic DIP and a 28-lead SOIC package.
FUNCTIONAL DESCRIPTION
The two analog input amplifiers (NORM, AUX) are internally biased by an on-chip voltage reference in order to allow operation of the AD28msp02 with a single +5 V power supply. An analog multiplexer selects either the NORM or AUX amplifier as the input to the ADC's sigma-delta modulator. The optional 20 dB preamplifier may be used to increase the signal level; the preamplifier can be inserted before the modulator or can be bypassed. Input signal level to the sigma-delta modulator should not exceed VINMAX, which is specified under "Analog Interface Electrical Characteristics." Refer to "Analog Input" in the "Design Considerations" section of this data sheet for more information. The input multiplexer and 20 dB preamplifier are configured by Bits 0 and 1 (IPS, IMS) of the AD28msp02's control register. If the multiplexer setting is changed while an input signal is being processed, the ADC's output must be allowed time to settle to ensure that the output data is valid.
ADC
Figure 1 shows a block diagram of the AD28msp02.
A/D CONVERSION
The ADC consists of a 2nd-order analog sigma-delta modulator, an anti-aliasing decimation filter, and a digital high-pass filter. The sigma-delta modulator noise-shapes the signal and produces 1-bit samples at a 1.0 MHz rate. This bit stream, which represents the analog input signal, is fed to the anti-aliasing decimation filter.
Decimation Filter
The A/D conversion circuitry of the AD28msp02 consists of two analog input amplifiers, an optional 20 dB preamplifier, and a sigma-delta analog-to-digital converter (ADC). The analog input signal to the AD28msp02 must be ac-coupled.
The anti-aliasing decimation filter contains two stages. The first stage is a sinc4 digital filter that increases resolution to 16 bits and reduces the sample rate to 40 kHz. The second stage is an IIR low-pass filter.
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AD28msp02
VFB NORM VIN NORM NORM INPUT AMP VFB AUX VIN AUX AUX INPUT AMP VOLTAGE REFERENCE CONTROL REGISTER SERIAL PORT SCLK 16-BIT SIGMA-DELTA DAC VOUT P PGA VOUTN OUTPUT DIFFERENTIAL AMP ANALOG SMOOTHING FILTER 1 1.0 MHz DIGITAL SIGMA-DELTA MODULATOR 16 1.0 MHz ANTI-IMAGING INTERPOLATION FILTER 16 8.0 kHz DIGITAL HIGH-PASS FILTER 16 SDI 8.0 kHz SDIFS MUX +20dB AMP 16-BIT SIGMA-DELTA ADC ANALOG SIGMA-DELTA MODULATOR 1 ANTI-ALIASING DECIMATION FILTER 16 DIGITAL HIGH-PASS FILTER 16 SDO 8.0 kHz DATA/ CNTRL SDOFS
1.0 MHz
8.0 kHz
V REF
CS
Figure 1. AD28msp02 Block Diagram
The IIR low-pass filter is a 10th-order elliptic filter with a passband edge at 3.7 kHz and a stopband attenuation of 65 dB at 4 kHz. This filter has the following specifications: Filter type: Sample frequency: Passband cutoff:* Passband ripple: Stopband cutoff: Stopband ripple: 10th-order low-pass elliptic IIR 40.0 kHz 3.70 kHz ± 0.2 dB 4.0 kHz 65.00 dB
The high-pass filter is a 4th-order elliptic filter with a passband cutoff at 150 Hz. Stopband attenuation is 25 dB. This filter has the following specifications: Filter type: Sample frequency: Passband cutoff: Passband ripple: Stopband cutoff: Stopband ripple: 4th-order high-pass elliptic IIR 8.0 kHz 150.0 Hz ± 0.2 dB 100.0 Hz 25.00 dB
*The passband cutoff frequency is defined to be the last point in the passband that meets the passband ripple specification. (Note that these specifications apply only to this filter, and not to the entire ADC. The specifications can be used to perform further analysis of the exact characteristics of the filter, for example using a digital filter design software package.)
(Note that these specifications apply only to this filter, and not to the entire ADC. The specifications can be used to perform further analysis of the exact characteristics of the filter, for example using a digital filter design software package.)
Figure 3 shows the frequency response of the high-pass filter.
0
Figure 2 shows the frequency response of the IIR low-pass filter.
0
20
LOG MAGNITUDE dB
20
LOG MAGNITUDE dB
40
40
60
60
80
80
100 0 60 120 180 FREQUENCY Hz 240 300
100 2000
2600
3200
3800
4400
5000
FREQUENCY Hz
Figure 3. High-Pass Filter Frequency Response
Figure 2. IIR Low-Pass Filter Frequency Response
High-Pass Filter
Passband ripple is ± 0.2 dB for the combined effects of the ADC's digital filters (i.e., high-pass filter and IIR low-pass of the decimation filter) in the 300 Hz3400 Hz passband. The output of the ADC is transferred to the AD28msp02's serial port (SPORT) at an 8 kHz rate, for transmission to the host DSP processor. Maximum group delay in the ADC will not exceed 1 ms in the region from 300 Hz to 3 kHz.
The digital high-pass filter removes frequency components at the low end of the spectrum; it attenuates signal energy below the passband of the converter. The high-pass filter can be bypassed by setting the ADBY bit (Bit 3) of the AD28msp02's control register.
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AD28msp02
PIN DESCRIPTIONS D/A CONVERSION
Pin Name VINNORM V F B NORM V I N AUX V F BAUX VOUTP VOUTN V REF MCLK
I/O/Z Function I O I O O O O I Analog input to inverting terminal of NORM input amplifier. Output terminal of NORM amplifier. Analog input to inverting terminal of AUX input amplifier. Output terminal of AUX amplifier. Analog output from noninverting terminal of differential output amplifier. Analog output from inverting terminal of differential output amplifier. On-chip bandgap voltage reference (2.5 V ± 10%). Master clock input; frequency must equal 13.0 MHz to guarantee listed specifications. Serial clock used to clock data or control bits to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the master clock (MCLK) divided by 5. SCLK is 3-stated when CS is low. Serial data input of SPORT. Both data and control information are input on this pin. Input at SDI is ignored when CS is low. Serial data output of SPORT. Both data and control information are output on this pin. SDO is 3-stated when CS is low. Framing signal for SDI serial transfers. Input at SDIFS is ignored when CS is low. Framing signal for SDO serial transfers. SDOFS is 3-stated when CS is low. Configures AD28msp02 for either data or control information transfers (via SPORT). Active-high chip select. Can be used to 3-state the SPORT interface; when CS is low, the SCLK, SDO, and SDOFS outputs are 3-stated and the SDI and SDIFS inputs are ignored. If CS is deasserted during a serial data transfer, the 16-bit word being transmitted is lost. Active low reset signal; resets Control Register and clears digital filters. RESET does not 3-state the SPORT outputs (SCLK, SDO, SDOFS). Analog supply voltage; nominal +5 V. Analog ground. Digital supply voltage; nominal +5 V. Digital ground.
The D/A conversion circuitry of the AD28msp02 consists of a sigma-delta digital-to-analog converter (DAC), an analog smoothing filter, a programmable gain amplifier, and a differential output amplifier.
DAC
The AD28msp02's sigma-delta DAC implements digital filters and a sigma-delta modulator with the same characteristics as the filters and modulator of the ADC. The DAC consists of a digital high-pass filter, an anti-imaging interpolation filter, and a digital sigma-delta modulator. The DAC receives 16-bit samples from the host DSP processor via AD28msp02's serial port at an 8 kHz rate. If the host processor fails to write a new value to the serial port, the existing (previous) data is read again. The data stream is filtered first by the DAC's high-pass filter and then by the anti-imaging interpolation filter. These filters have the same characteristics as the ADC's anti-aliasing decimation filter and digital high-pass filter. The output of the interpolation filter is fed to the DAC's digital sigma-delta modulator, which converts the 16-bit data to 1-bit samples at a 1.0 MHz rate. The modulator noise-shapes the signal such that errors inherent to the process are minimized in the passband of the converter. The bit stream output of the sigmadelta modulator is fed to the AD28msp02's analog smoothing filter where it is converted to an analog voltage.
High-Pass Filter
SCLK
O/Z
SDI
I
SDO
O/Z
SDIFS
I
The digital high-pass filter of the AD28msp02's DAC has the same characteristics as the high-pass filter of the ADC. The high-pass filter removes frequency components at the low end of the spectrum; it attenuates signal energy below the passband of the converter. The DAC's high-pass filter can be bypassed by setting the DABY bit (Bit 2) of the AD28msp02's control register. The high-pass filter is a 4th-order elliptic filter with a passband cutoff at 150 Hz. Stopband attenuation is 25 dB. This filter has the following specifications: Filter type: Sample frequency: Passband cutoff: Passband ripple: Stopband cutoff: Stopband ripple: 4th-order high-pass elliptic IIR 8.0 kHz 150.0 Hz ± 0.2 dB 100.0 Hz 25.00 dB
SDOFS
O/Z
DATA/CNTRL I
CS
I
(Note that these specifications apply only to this filter, and not to the entire DAC. The specifications can be used to perform further analysis of the exact characteristics of the filter, for example using a digital filter design software package.)
Figure 3 shows the frequency response of the high-pass filter.
Interpolation Filter
RESET
I
V CC GNDA V DD GND D
The anti-imaging interpolation filter contains two stages. The first stage is an IIR low-pass filter that interpolates the data rate from 8 kHz to 40 kHz and removes images produced by the interpolation process. The output of this stage is then interpolated to 1.0 MHz and fed to the second stage, a sinc4 digital filter that attenuates images produced by the 40 kHz to 1.0 MHz interpolation process.
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AD28msp02
The IIR low-pass filter is a 10th-order elliptic filter with a passband edge at 3.70 kHz and a stopband attenuation of 65 dB at 4 kHz. This filter has the following specifications: Filter type: Sample frequency: Passband cutoff:* Passband ripple: Stopband cutoff: Stopband ripple: l0th-order low-pass elliptic IIR 40.0 kHz 3.70 kHz ± 0.2 dB 4.0 kHz 65.00 dB
SERIAL PORT
The AD28msp02 communicates with a host processor via the bidirectional synchronous serial port (SPORT). The SPORT is used to transmit and receive digital data and control information. All serial transfers are 16 bits long, MSB first. Data bits are transferred at the serial clock rate (SCLK). SCLK equals the master clock frequency divided by 5. SCLK = 2.6 MHz for the master clock frequency MCLK = 13.0 MHz.
Host Processor Interface
*The passband cutoff frequency is defined to be the last point in the passband that meets the passband ripple specification. (Note that these specifications apply only to this filter, and not to the entire DAC. The specifications can be used to perform further analysis of the exact characteristics of the filter, for example using a digital filter design software package.)
The AD28msp02-to-host processor interface is shown in Figure 4.
AD28msp02
SDO SDOFS SCLK DATA/CNTRL SDI SDIFS
Host Processor
SERIAL DATA RECEIVE RECEIVE FRAME SYNC SERIAL CLOCK FLAG SERIAL DATA TRANSMIT TRANSMIT FRAME SYNC
Figure 2 shows the frequency response of the IIR low-pass filter. Passband ripple is ± 0.2 dB for the combined effects of the DAC's digital filters (i.e., high-pass filter and IIR low pass of the interpolation filter) in the 300 Hz3400 Hz passband.
Analog Smoothing Filter and Programmable Gain Amplifier
The programmable gain amplifier (PGA) can be used to adjust the output signal level by 15 dB to +6 dB. This gain is selected by bits 79 (OG0, OG1, OG2) of the AD28msp02's control register. The AD28msp02's analog smoothing filter consists of a 2ndorder Sallen-Key continuous-time filter and a 3rd-order switched capacitor filter. The Sallen-Key filter has a 3 dB point at approximately 80 kHz.
Differential Output Amplifier
Figure 4. AD28msp02-to-Host Processor Interface
Table I describes the SPORT signals and how they are used to communicate with the host processor. The AD28msp02's chip select (CS) must be held high to enable SPORT operation. CS can be used to 3-state the SPORT pins and disable communication with the host processor. To use the ADSP-2101 or ADSP-2111 as host DSP processor for the AD28msp02, the following connections can be used (as shown in Figure 5): AD28msp02 Pin SCLK SDO SDOFS SDI SDIFS DATA/CNTRL ADSP-2101/2111 Pin SCLK0 DR0 RFS0 DT0 TFS0 FO (Flag Output)
The AD28msp02's analog output (VOUTP, VOUTN) is produced by a differential output amplifier. The differential amplifier can drive loads of 2 k or greater and has a maximum differential output voltage swing of ± 3.156 V peak-to-peak (3.17 dBm0). The output signal is dc-biased to the AD28msp02's on-chip voltage reference (VREF) and can be ac-coupled directly to a load or dc-coupled to an external amplifier. Refer to "Analog Output" in the "Design Considerations" section of this data sheet for more information. The VOUTPVOUTN outputs must be used as differential outputs; do not use either as a single-ended output.
Table I. SPORT Signals
Signal Name SCLK SDO SDOFS SDI SDIFS
Description Serial clock Serial data output Serial data output frame sync Serial data input Serial data input frame sync
Generated By AD28msp02 AD28msp02 AD28msp02 Host Processor Host Processor
Signal State When RESET Low (CS High) Low Low Low -- --
Signal State During Powerdown (CS High) Active Active* Low -- --
(CS must be held high to enable SPORT operation.)
*Outputs last data value that was valid prior to entering powerdown.
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AD28msp02
Note that the ADSP-2101's SPORT0 communicates with the AD28msp02's SPORT while the ADSP-2101's Flag Output (FO) is used to signal the AD28msp02's DATA/CNTRL input. SPORT1 on the ADSP-2101 must be configured for flags and interrupts in this system. Figure 6 shows an ADSP-2101 assembly language program that initializes the AD28msp02 and implements digital loopback through the DSP processor.
AD28msp02
SDO SDOFS DR0 RFS0 SCLK0 FO DT0 TFS0
ADSP-2101
SCLK DATA/CNTRL SDI SDIFS
Figure 5. AD28msp02-to-ADSP-2101 Interface
{ This ADSP-2101 program initializes the AD28msp02 } { and executes a loopback, or talk-through, routine. } .MODULE/ABS = 0/BOOT = 0 test1; resetv: irq2v: st0x: sr0x: JUMP begin; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; ax0 = rx0; tx0 = ax0; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RESET FLAG OUT; AX0 = 0x2A0F; DM (0x3FF6) = AX0; AX0 = 0x101F; DM (0x3FFF) = AX0; IMASK= 0x10; AX0 = 0x30; TX0 = AX0; IDLE; NOP; IMASK= 0x08; SET FLAG OUT; wait: JUMP wait; NOP; { Wait for receive interrupt } {restart} {IRQ2} {SPORT0 Tx} {SPORT0 Rx}
irq1v: irq0v: timerv: begin:
{irq1} {irq0}
{Configure ADSP-2101 SPORT0 for } { ext. SCLK, ext. RFS, int. TFS } { Enable ADSP-2101 SPORT0, } { configure SPORT1 for Flag Out } { Write control word to take} { AD28msp02 out of powerdown }
.ENDMOD;
Figure 6. ADSP-2101 Digital Loopback Routine
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