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Details, datasheet, quote on part number:AD2S80ASD
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Datasheet text preview:
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FEATURES Monolithic (BiMOS ll) Tracking R/D Converter 40-Pin DIP Package 44-Pin LCC Package 10-,12-,14- and 16-Bit Resolution Set by User Ratiometric Conversion Low Power Consumption: 300 mW typ Dynamic Performance Set by User High Max Tracking Rate 1040 RPS (10 Bits) Velocity Output Industrial Temperature Range Versions Military Temperature Range Versions ESD Class 2 Protection (2,000 V min) /883 B Parts Available APPLICATIONS DC Brushless and AC Motor Control Process Control Numerical Control of Machine Tools Robotics Axis Control Military Servo Control GENERAL DESCRIPTION
Variable Resolution, Monolithic Resolver-to-Digital Converter AD2S80A
FUNCTIONAL BLOCK DIAGRAM
AC ERROR O/P INTEGRATOR I/P
INTEGRATOR O/P VCO I/P
DEMOD I/P
AD2S80A
SIN I/P SIG GND COS I/P ANALOG GND RIPPLE CLK +12V 12V DATA LOAD OUTPUT DATA LATCH A2 A1 SEGMENT SWITCHING R-2R DAC A3 PHASE SENSITIVE DETECTOR
16-BIT UP/DOWN COUNTER
VCO DATA TRANSFER LOGIC
SC1
ENABLE
SC2
BYTE SELECT +5V DIG GND BUSY
DEMOD O/P DIR
16 DATA BITS
PRODUCT HIGHLIGHTS
The AD2S80A is a monolithic 10-, 12-, 14- or 16-bit tracking resolver-to-digital converter contained in a 40-pin DIP or 44pin LCC ceramic package. It is manufactured on a BiMOS II process that combines the advantages of CMOS logic and bipolar high accuracy linear circuits on the same chip. The converter allows users to select their own resolution and dynamic performance with external components. This allows the users great flexibility in defining the converter that best suits their system requirements. The converter allows users to select the resolution to he 10, 12, 14 or 16 bits and to track resolver signals rotating at up to 1040 revs per second (62,400 rpm) when set to 10-bit resolution. The AD2S80A converts resolver format input signals into a parallel natural binary digital word using a ratiometric tracking conversion method. This ensures high-noise immunity and tolerance of lead length when the converter is remote from the resolver. The 10-, 12-, 14- or 16-bit output word is in a three-state digital logic available in 2 bytes on the 16 output data lines. BYTE SELECT, ENABLE and INHIBIT pins ensure easy data transfer to 8- and 16-bit data buses, and outputs are provided to allow for cycle or pitch counting in external counters. An analog signal proportional to velocity is also available and can be used to replace a tachogenerator. The AD2S80A operates over 50 Hz to 20,000 Hz reference frequency. REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Monolithic. A one chip solution reduces the package size required and increases the reliability. Resolution Set by User. Two control pins are used to select the resolution of the AD2S80A to be 10, 12, 14 or 16 bits allowing the user to use the AD2S80A with the optimum resolution for each application. Ratiometric Tracking Conversion. Conversion technique provides continuous output position data without conversion delay and is insensitive to absolute signal levels. It also provides good noise immunity and tolerance to harmonic distortion on the reference and input signals. Dynamic Performance Set by the User. By selecting external resistor and capacitor values the user can determine bandwidth, maximum tracking rate and velocity scaling of the converter to match the system requirements. The external components required are all low cost preferred value resistors and capacitors, and the component values are easy to select using the simple instructions given. Velocity Output. An analog signal proportional to velocity is available and is linear to typically one percent. This can be used in place of a velocity transducer in many applications to provide loop stabilization in servo controls and velocity feedback data. Low Power Consumption. Typically only 300 mW. Military Product. The AD2S80A is available processed in accordance with MIL-STD-883B, Class B. MODELS AVAILABLE Information on the models available is given in the section "Ordering Information."
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
INHIBIT
AD2S80ASPECIFICATIONS (typical at +25 C unless otherwise noted)
Parameter SIGNAL INPUTS Frequency Voltage Level Input Bias Current Input Impedance Maximum Voltage REFERENCE INPUT Frequency Voltage Level Input Bias Current Input Impedance CONTROL DYNAMICS Repeatability Allowable Phase Shift Tracking Rate Conditions Min 50 1.8 1.0 8 50 1.0 60 1.0 1 +10 1040 260 65 16.25 20,000 8.0 150 AD2S80A Typ Max 20,000 2.2 150 Units Hz V rms nA M V pk Hz V pk nA M LSB Degrees rps rps rps rps 2.0 60
B a n d w i d t h1 ACCURACY Angular Accuracy Monotonicity Missing Codes (16-Bit Resolution) VELOCITY SIGNAL Linearity Reversion Error DC Zero Offset2 DC Zero Offset Tempco Gain Scaling Accuracy Output Voltage Dynamic Ripple Output Load INPUT/OUTPUT PROTECTION Analog Inputs Analog Outputs DIGITAL POSITION Resolution Output Format Load INHIBIT 3 Sense Time to Stable Data ENABLE
3
(Signals to Reference) 10 Bits 12 Bits 14 Bits 16 Bits User Selectable A, J, S B, K, T L, U Guaranteed Monotonic A, B, J, K, S, T L, U Over Full Range
10
8 +1 LSB 4 +1 LSB 2 +1 LSB 4 1 ±1 ±1 22 3 ±2 6 ± 10 ± 10.5 1.5 1.0
arc min arc min arc min Codes Code % FSD % FSD mV µV/°C % FSD V % rms O/P k V mA
1 mA Load Mean Value
±8
±9
Overvoltage Protection Short Circuit O/P Protection 10, 12, 14, and 16 Bidirectional Natural Binary
± 5.6
±8 ±8
± 10.4
3 Logic LO to Inhibit 600 Logic LO Enables Position Output. Logic HI Outputs in High Impedance State MS Byte DB1DB8, LS Byte DB9DB16 LS Byte DB1DB8, LS Byte DB9DB16 60 Internally Pulled High (100 k) to +VS 10 Bit 12 Bit 14 Bit 16 Bit 140
LSTTL
ns
ENABLE Time BYTE SELECT Sense LOGIC LO Time to Data Available SHORT CYCLE INPUTS SC1 SC2 0 0 0 1 1 0 1 1
3
35
110
ns
ns
2
REV. A
AD2S80A
Parameter DATA LOAD Sense Conditions Internally Pulled High (100 k) to +VS. Logic LO Allows Data to be Loaded into the Counters from the Data Lines Logic HI When Position O/P Changing 200 Use Additional Pull-Up Logic HI Counting Up Logic LO Counting Down 3
3
Min
AD2S80A Typ Max 150 300
Units ns
BUSY 3 Sense Width Load DIRECTION 3 Sense Max Load RIPPLE CLOCK Sense Width Reset Load DIGITAL INPUTS High Voltage, VIH Low Voltage, VIL
600 1
ns LSTTL
LSTTL
Logic HI All 1s to All 0s All 0s to All 1s Dependent on Input Velocity Before Next Busy
300 3 LSTTL V 0.8 V
INHIBIT, ENABLE DB1DB16, Byte Select ± VS = ± 10.8 V, VL = 5.0 V INHIBIT, ENABLE DB1DB16, Byte Select ± VS = ± 13.2 V, VL = 5.0 V INHIBIT, ENABLE DB1DB16 ± VS = ± 13.2 V , VL = 5.5 V INHIBIT, ENABLE DB1DB16, Byte Select ± VS = ± 13.2 V, VL = 5.5 V ENABLE = HI SC1, SC2, Data Load ± VS = ± 12.0 V, VL = 5.0 V ENABLE = HI SC1, SC2, Data Load ± VS = ± 12.0 V, VL = 5.0 V DB1DB16 RIPPLE CLK, DIR ± VS = ± 12.0 V, VL = 4.5 V IOH = 100 µA DB1DB16 RIPPLE CLK, DIR ± VS = ± 12.0 V, VL = 5.5 V IOL = 1.2 mA DB1DB16 Only ± VS = ± 12.0 V, VL = 5.5 V V OL = 0 V ± VS = ± 12.0 V, VL = 5.5 V VOH = 5.0 V
2.0
DIGITAL INPUTS High Current, IIH Low Current, IIL
± 100 ± 100
µA µA
DIGITAL INPUTS Low Voltage, VIL Low Current, IIL
1.0 400
V µA
DIGITAL OUTPUTS High Voltage, VOH
2.4
V
Low Voltage, VOL
0.4
V
THREE-STATE LEAKAGE Current IL
± 100 ± 100
µA µA
NOTES 1 Refer to small signal bandwidth. 2 Output offset dependent on value for R6. 3 Refer to timing diagram. Specifications subject to change without notice. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
REV. A
3
AD2S80ASPECIFICATIONS (typical at +25 C unless otherwise noted)
Parameter RATIO MULTIPLIER AC Error Output Scaling Conditions 10 Bit 12 Bit 14 Bit 16 Bit Min AD2S80A Typ Max 177.6 44.4 11.1 2.775 12 w.r.t. REF w.r.t. REF 0.882 1 0.9 60 0.918 ± 0.02 150 ±8 63 100 1 60 5 150 Units mV/Bit mV/Bit mV/Bit mV/Bit mV V rms/V dc V rms/V dc nA M V dB nA/LSB mV nA V
PHASE SENSITIVE DETECTOR Output Offset Voltage Gain In Phase In Quadrature Input Bias Current Input Impedance Input Voltage INTEGRATOR Open-Loop Gain Dead Zone Current (Hysteresis) Input Offset Voltage Input Bias Current Output Voltage Range VCO Maximum Rate VCO Rate VCO Power Supply Sensitivity Increase Decrease Input Offset Voltage Input Bias Current Input Bias Current Tempco Input Voltage Range Linearity of Absolute Rate Full Range Over 0% to 50% of Full Range Reversion Error Sensitivity of Reversion Error to Symmetry of Power Supplies POWER SUPPLIES Voltage Levels +VS V S +V L Current ± IS ± IS ± IL
At 10 kHz
57
± VS = ± 10.8 V dc ± VS = ± 12 V dc Positive Direction Negative Direction +V S V S +V S V S
±7
7.1 7.1
7.9 7.9 +0.5 8.0 8.0 +2.0 1 70 1.22
1.1 8.7 8.7
MHz kHz/µA kHz/µA %/V %/V %/V %/V mV nA nA/ ° C V % FSD % FSD % FSD %/V of Asymmetry
5 380 ±8 <2 <1 1.5
±8
+10.8 10.8 +5 ± V S @ ± 12 V ± VS @ 13.2 V +V L @ ± 5.0 V 12 19 0.5
+13.2 13.2 +13.2 23 30 1.5
V V V mA mA mA
Specification subject to change without notice. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
ESD SENSITIVITY The AD2S80A features an input protection circuit consisting of large "distributed" diodes and polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast, low energy pulses (Charges Device Model). The AD2S80A is ESD protection Class II (2000 V min). Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. For further information on ESD precautions, refer to Analog Devices ESD Prevention Manual.
WARNING!
ESD SENSITIVE DEVICE
4
REV. A
AD2S80A
Power Supply Voltage (+VS, VS) . . . . . . . . . ± 12 V dc ± 10% Power Supply Voltage VL . . . . . . . . . . . . . . . . . +5 V dc ± 10% Analog Input Voltage (SIN and COS) . . . . . . . 2 V rms ± 10% Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak Signal and Reference Harmonic Distortion . . . . . . . 10% (max) Phase Shift Between Signal and Reference . . . ± 10 Degrees (max) Ambient Operating Temperature Range Commercial (JD, KD, LD) . . . . . . . . . . . . . . 0°C to +70°C Industrial (AD, BD) . . . . . . . . . . . . . . . . . . . 40°C to +85°C Extended (SD, SE, TD, TE, UD, UE) . . . 55°C to +125°C
ABSOLUTE MAXIMUM RATINGS l (with respect to GND)
2
RECOMMENDED OPERATING CONDITIONS
PIN CONFIGURATIONS
REFERENCE I/P DEMOD I/P 1 2 3 4 5 6 7 8 9 40 DEMOD O/P 39 INTEGRATOR O/P 38 INTEGRATOR I/P 37 VCO I/P 36 VS 35 RIPPLE CLK 34 DIRECTION 33 BUSY 32 DATA LOAD
DIP (D) Package
AC ERROR O/P COS ANALOG GND SIGNAL GND SIN +VS MSB DB1
DB2 10
31 SC2 TOP VIEW DB3 11 (Not to Scale) 30 SC1 29 DIGITAL GND 28 INHIBIT 27 BYTE SELECT 26 ENABLE 25 VL 24 DB16 LSB 23 DB15 22 DB14 21 DB13
AD2S80A
DB4 12 DB5 13 DB6 14 DB7 15 DB8 16 DB9 17 DB10 18 DB11 19 DB12 20
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V dc VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V dc +VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to VS SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to VS COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to VS Any Logical Input .. . . . . . . . . . . . . . . . . . . 0.4 V dc to +VL dc Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . +14 V to VS Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to VS VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to VS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 mW Operating Temperature Commercial (JD, KD, LD) . . . . . . . . . . . . . . 0°C to +70°C Industrial (AD, BD) . . . . . . . . . . . . . . . . . . . 40°C to +85°C Extended (SD, SE, TD, TE, UD, UE) . . . 55°C to +125°C JC3 (40-Pin DIP 883 Parts Only) . . . . . . . . . . . . . . . . 11°C/W JC3 (44-Pin LCC 883 Parts Only) . . . . . . . . . . . . . . . . 10°C/W Storage Temperature (All Grades) . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
CAUTION: 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur. 2. Correct polarity voltages must be maintained on the +V S and VS pins. 3. With reference to Appendix C of MIL-M-38510.
INTEGRATOR O/P
AC ERROR O/P
SIGNAL GND
DEMOD I/P
INTEGRATOR I/P
REFERENCE I/P
ANALOG GND
DEMOD O/P
COS
VCO I/P
6 SIN 7 +VS 8 NC 9 MSB DB1 10 DB2 11 DB3 12 DB4 13 DB5 14 DB6 15 DB7 16 DB8 17
5
4
3
2
1 44 43 42 41 40 39 VS 38 RIPPLE CLOCK 37 DIRECTION 36 BUSY
NC
LCC (E) Package
AD2S80A
TOP VIEW (Not to Scale)
35 DATA LOAD 34 NC 33 SC2 32 SC1 31 DIGITAL GND 30 INHIBIT 29 NC
18 19 20 21 22 23 24 25 26 27 28
DB9
LSB DB16
NC = NO CONNECT
Bit Weight Table
Binary Bits (N) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Resolution (2N) 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 116384 32768 65536 131072 262144 Degrees /Bit 360.0 180.0 90.0 45.0 22.5 11.25 5.625 2.8125 1.40625 0.703125 0.3515625 0.1757813 0.0878906 0.0439453 0.0219727 0.0109836 0.0054932 0.0027466 0.0013733 Minutes /Bit 21600.0 10800.0 5400.0 2700.0 1350.0 675.0 337.5 168.75 84.375 42.1875 21.09375 10.546875 5.273438 2.636719 1.318359 0.659180 0.329590 0.164795 0.082397 Seconds /Bit 1296000.0 648000.0 324000.0 162000.0 81000.0 40500.0 20250.0 10125.0 5062.5 2531.25 1265.625 632.8125 316.40625 158.20313 79.10156 39.55078 19.77539 9.88770 4.94385
PIN DESIGNATIONS
MNEMONIC REFERENCE I/P DEMOD I/P AC ERROR O/P COS ANALOG GROUND SIGNAL GROUND SIN +VS DB1DB16 VL ENABLE DESCRIPTION REFERENCE SIGNAL INPUT DEMODULATOR INPUT RATIO MULTIPLIER OUTPUT COSINE INPUT POWER GROUND RESOLVER SIGNAL GROUND SINE INPUT POSITIVE POWER SUPPLY PARALLEL OUTPUT DATA LOGIC POWER SUPPLY LOGIC Hl-OUTPUT DATA IN HIGH IMPEDANCE STATE, LOGIC LO PRESENTS DATA TO THE OUTPUT LATCHES LOGIC Hl-MOST SIGNIFICANT BYTE TO DB1DB8 LOGIC LO-LEAST SlGNlFlCANT BYTE TO DB1DB8 LOGIC LO INHIBITS DATA TRANSFER TO OUTPUT LATCHES DlGITAL GROUND SELECT CONVERTER RESOLUTION LOGIC LO DB1DB16 INPUTS LOGIC Hl DB1D16 OUTPUTS CONVERTER BUSY, DATA NOT VALID WHILE BUSY Hl LOGIC STATE DEFINES DIRECTION OF INPUT SIGNAL ROTATION POSITIVE PULSE WHEN CONVERTER OUTPUT CHANGES FROM 1S TO ALL 0S OR VICE VERSA NEGATIVE POWER SUPPLY VCO INPUT INTEGRATOR INPUT INTEGRATOR OUTPUT DEMODULATOR OUTPUT
BYTE SELECT INHIBIT DIGITAL GROUND SC1SC2 DATA LOAD BUSY DIRECTION RIPPLE CLOCK VS VCO I/P INTEGRATOR I/P INTEGRATOR O/P DEMOD O/P
REV. A
5
BYTE SELECT
ENABLE
DB11
DB10
DB12
DB13
DB14
DB15
+VL
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