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Details, datasheet, quote on part number:AD5222BRU1M
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Datasheet text preview:
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FEATURES 128-Position, 2-Channel Potentiometer Replacement 10 k , 50 k , 100 k , 1 M V ery Low Power: 40 A Max 2.7 V Dual Supply Operation or 2.7 V to 5.5 V Single Supply Operation Increment/Decrement Count Control APPLICATIONS Stereo Channel Audio Level Control Mechanical Potentiometer Replacement Remote Incremental Adjustment Applications Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Line Impedance Matching
Increment / Decrement Dual Digital Potentiometer AD5222
FUNCTIONAL BLOCK DIAGRAM
VDD U/D
AD5222
UP/DOWN COUNTER DECODE
A1 W1 B1
POR CS MODE DACSEL CLK GND A2 UP/DOWN COUNTER DECODE W2 B2 VSS
DAC SELECT AND ENABLE
GENERAL DESCRIPTION
The AD5222 provides a dual channel, 128-position, digitally controlled variable-resistor (VR) device. This device performs the same electronic adjustment function as a potentiometer or variable resistor. These products were optimized for instrument and test equipment push-button applications. Choices between bandwidth or power dissipation are available as a result of the wide selection of end-to-end terminal resistance values. The AD5222 contains two fixed resistors with wiper contacts that tap the fixed resistor value at a point determined by a digitally controlled up/down counter. The resistance between the wiper and either end point of the fixed resistor provides a constant r esistance step size that is equal to the end-to-end resistance d ivided by the number of positions (e.g., R STEP = 10 k/128 = 78 ). The variable resistor offers a true adjustable value of resistance, between Terminal A and the wiper, or Terminal B and the wiper. The fixed A-to-B terminal resistance of 10 k , 50 k, 100 k , or 1 M has a nominal temperature coefficient of 35 ppm/°C. The chip select CS, count CLK and U/D direction control inputs set the variable resistor position. The MODE determines whether b o t h VRs are incremented together or independently. With MODE at logic zero, both wipers are incremented UP or DOWN without changing the relative settings between the wipers. Also, the relative ratio between the wipers is preserved if either wiper reaches the end of the resistor array. In the independent MODE (Logic 1) only the VR determined by the DACSEL pin is changed. DACSEL (Logic 0) changes RDAC 1. These inputs, which control the internal up/down counter, can be easily generated with
m e c h a n i c a l or push-button switches (or other contact closure devices). This simple digital interface eliminates the need for microcontrollers in front panel interface designs. The AD5222 is available in the surface-mount (SO-14) package. For ultracompact solutions, selected models are available in the thin TSSOP-14 package. All parts are guaranteed to operate o v e r the extended industrial temperature range of 40°C to +85°C. For 3-wire, SPI-compatible interface applications, see the AD5203/AD5204/AD5206, AD7376, and AD8400/AD8402/ AD8403 products.
5V VDD CS U/D U/D CLK INCREMENT A1 W1 B1
A2 DACSEL MODE GND W2 B2 VSS
Figure 1. Typical Push-Button Control Application
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999
V 10% or 5 V AD5222SPECIFICATIONS u(Vnles=s 3otherwise noted.)
DD
10%, VSS = 0 V, VA = +VDD, VB = 0 V, 40 C < TA < +85 C,
Min 1 1 30 Typ1 Max ± 1/4 +1 ± 0.4 +1 +30 35 45 100 0.2 1 Unit LSB LSB % ppm/ °C % Bits LSB LSB LSB ppm/ °C LSB LSB V pF pF nA
Parameter
Symbol
Condition
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) R-DNL RWB, VA = NC Resistor Differential NL2 Resistor Nonlinearity2 R-INL RWB, VA = NC Nominal Resistor Tolerance R VAB = VDD, Wiper = No Connect, T A = 25°C Resistance Temperature Coefficient RAB/T VAB = VDD, Wiper = No Connect Wiper Resistance3 RW IW = VDD /R, VDD = 3 V or 5 V Nominal Resistance Match R/RO CH 1 to 2, V AB = VDD, TA = 25°C DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs) Resolution N INL RAB = 10 k, 50 k, or 100 k Integral Nonlinearity4 INL RAB = 1 M Differential Nonlinearity4 DNL Voltage Divider Temperature Coefficient VW / T Code = 40H Full-Scale Error V WFSE Code = 7F H Zero-Scale Error V WZSE Code = 00H RESISTOR TERMINALS Voltage Range 5 Capacitance6 A, B C a p a c i t a n c e6 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Single-Supply Range Power Dual-Supply Range Positive Supply Current Negative Supply Current Power Dissipation 7 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 8, 9 Bandwidth 3 dB VA, B, W CA, B CW ICM V IH V IL IIL CIL VDD RANGE VDD/SS RANGE IDD ISS P DISS PSS BW_10K BW_50K BW_100K BW_1M THDW tS e N_WB
7 1 2 1 1 0 V SS
± 1/4 ± 1/2 ± 1/4 20 0.5 0.5
+1 +2 +1 +0 1 V DD
f = 1 MHz, Measured to GND, Code = 40 H f = 1 MHz, Measured to GND, Code = 40 H VA = V B = V W VDD = 5 V/3 V VDD = 5 V/3 V VIN = 0 V or 5 V 2.4/2.1
45 60 1
5 V SS = 0 V VIH = 5 V or VIL = 0 V VSS = 2.5 V, VDD = +2.7 V VIH = 5 V or VIL = 0 V, VDD = 5 V 2.7 ± 2.3
V 0.8/0.6 V ±1 µA pF V V µA µA µW %/% kHz kHz kHz kHz % µs nVHz ns ns ns ns ns ns ns ns ns
5.5 ± 2.7 15 40 15 40 150 400 0.002 0.05 1000 180 78 7 0.005 2 14
Total Harmonic Distortion VW Settling Time Resistor Noise Voltage
RAB = 10 k, Code = 40 H RAB = 50 k, Code = 40 H RAB = 100 k, Code = 40H RAB = 500 k, Code = 40H VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz RAB = 10 k, ± 1 LSB Error Band RWB = 5 k, f = 1 kHz 30 20 20 10 30 20 30 20 40
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts) 6, 10 Input Clock Pulsewidth tCH, t CL Clock Level High or Low CS to CLK Setup Time t CSS CS Rise to CLK Hold Time t CSH U/D to Clock Fall Setup Time t UDS U/D to Clock Fall Hold Time t UDH DACSEL to Clock Fall Setup Time t DSS DACSEL to Clock Fall Hold Time t DSH MODE to Clock Fall Setup Time t MDS MODE to Clock Fall Hold Time t MDH
NOTES 1Typicals represent average readings at 25°C, V DD = 5 V. 2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 22 test circuit. 3Wiper resistance is not measured on the R AB = 1 M models. 4INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V = V W A DD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 21 test circuit. 5Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 6Guaranteed by design and not subject to production test. 7P DISS is calculated from (I DD × V DD). CMOS logic level inputs result in minimum power dissipation. 8Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 9All dynamic characteristics use V DD = 5 V. 10See timing diagram for location of measured values. All input control voltages are specified with t = t = 2.5 ns (10% to 90% of +3 V) and timed from a voltage level R F of 1.5 V. Switching characteristics are measured using both V DD = 5 V or V DD = 3 V. Specifications subject to change without notice.
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AD5222
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C, unless otherwise noted)
ORDERING GUIDE Kilo Package Package Ohms Temperature Description Option 10 10 50 50 100 100 1,000 1,000 40°C/+85°C 40°C/+85°C 40°C/+85°C 40°C/+85°C 40°C/+85°C 40°C/+85°C 40°C/+85°C 40°C/+85°C SO-14 TSSOP-14 SO-14 TSSOP-14 SO-14 TSSOP-14 SO-14 TSSOP-14 R-14 RU-14 R-14 RU-14 R-14 RU-14 R-14 RU-14
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 5 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VA, VB, V W to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD AX BX , AX WX , BX WX . . . . . . . . . . . . . . . . . . . ± 20 mA Digital Input Voltage to GND . . . . . . . . . . . . 0 V, VDD + 0.3 V Operating Temperature Range . . . . . . . . . . . 40°C to +85°C Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C Package Power Dissipation . . . . . . . . . . . . . (TJ max TA)/JA Thermal Resistance JA, SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
CS
Model AD5222BR10 AD5222BRU10 AD5222BR50 AD5222BRU50 AD5222BR100 AD5222BRU100 AD5222BR1M AD5222BRU1M
The AD5222 die size is 56 mil × 60 mil, 3360 sq. mil; 1.4224 mm × 1.524 mm, 2.1677 sq. mm. Contains 1503 transistors. Patent Number 5495245 applies.
PIN FUNCTION DESCRIPTIONS
Pin Name
tCSS tCH tCL tCSH
Description
CLK
tUDS
U/D
tUDH tDSS
1 2 3 4
DACSEL
tDSH tMDS
MODE
tMDH
Figure 2. Detail Timing Diagram
Truth Table
5 6 7 8 9 10
CS L L H
CLK t t X
U/ D H L X
Operation Wiper Increment Toward Terminal A Wiper Decrement Toward Terminal B Wiper Position Fixed 11 12 13 14
Common Mode (MODE = 0) moves both wipers together either UP or DOWN the resistor array without changing the relative distance between the wipers. Also, the distance between both wipers is preserved if either reaches the end of the array. Independent Mode (MODE = 1) allows user to control each RDAC individually: DACSEL = 0 sets RDAC1; DACSEL = 1: sets RDAC2.
B Terminal RDAC #1. A Terminal RDAC #1. Wiper RDAC #1, DACSEL = 0. Negative Power Supply. Specified for operation at both 0 V or 2.7 V (Sum of |VDD | + |VSS | < 5.5 V). W2 Wiper RDAC #2, DACSEL = 1. A2 A Terminal RDAC #2. B2 B Terminal RDAC #2. GND Ground. MODE Common MODE = 0, Independent MODE = 1. DACSEL DAC Select determines which wiper is increm e n t e d in the Independent MODE = 1. DACSEL = 0 sets RDAC1, DACSEL = 1 sets RDAC2. U/D UP/DOWN Direction Control. CLK Serial Clock Input, Negative Edge Triggered. CS Chip Select Input, Active Low. When CS is high, the UP/DOWN counter is disabled. V DD Positive Power Supply. Specified for operation at both +3 V or +5 V. (Sum of |VDD | + |VSS | < 5.5 V).
PIN CONFIGURATION
B1 1 A1 2 W1 3 14 VDD 13 CS
B1 A1 W1 V SS
VSS 4
12 CLK TOP VIEW 11 U/D (Not to Scale) W2 5 10 DACSEL
AD5222
A2 6 B2 7
9 MODE 8 GND
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5222 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD5222Typical Performance Characteristics
100 0.25 0.20 PERCENT OF NOMINAL END-TO-END RESISTANCE % RAB 0.15 75 R-DNL ERROR LSB 0.10 0.05 0 0.05 0.10 0.15 RWB 0 0 32 64 CODE Decimal 96 128 RWA 0.20 0.25 0 16 32 48 64 80 CODE Decimal 96 112 128 TA = +85 C VDD = +15V VSS = 15V RAB = 50k TA = +25 C TA = 55 C
50
25
Figure 3. Wiper-To-End Terminal Resistance vs. Code
Figure 6. R-DNL Relative Resistance Step Position Change vs. Code
5 4.5 4 VWB VOLTAGE V 3.5 3 2.5 2 1.5 1 0.5 0
3FH 20H 10H R-INL ERROR LSB 08H 05H
1.0 0.8 0.6 50k 0.4 0.2 0 0.2 100k 0.4 0.6 0.8 7 1.0 0 16 32 48 64 80 CODE Decimal 96 112 128 VERSION 1M VERSION VERSION 10k VERSION VDD/VSS = 2.7V/0V TA = 25 C
02H
RAB = 10k VDD = 5V TA = 25 C 0 1 2 3 4 IWA CURRENT mA 5 6
Figure 4. Resistance Linearity vs. Conduction Current
Figure 7. R-INL Resistance Nonlinearity Error vs. Code
180 SS = 600 UNITS VDD = 2.7V TA = 25 C
0.6 0.4 0.2 VDD/VSS = 2.7V/0V TA = 25 C 10k VERSION 50k VERSION
150
120 REQUENCY INL LSB 0 0.2 0.4 0.6 30 0.8 0 F 40 41 42 44 45 47 48 50 51 53 54 56 57 59 60 WIPER RESISTANCE 1.0 0 16 32 48 64 80 CODE Decimal 96 112 128 1M VERSION
90
60
100k
VERSION
Figure 5. Wiper Contact Resistance
Figure 8. Potentiometer Divider INL Error vs. Code
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AD5222
70 POTENTIOMETER MODE TEMPCO ppm/ C 60 50 40 30 20 10 0 10 20 30 0 16 32 48 64 80 CODE Decimal 96 112 128 1M VERSION 10k VERSION VDD/VSS = 2.7V/0V TA = 25 C 9 6 3 0 GAIN dB 3 6 9 12 15 18 21 100 B 00k BW 10k 50k 100k 1M 1k 764kHz 132kHz 64kHz 6.6kHz 100k 1M 1 F A W OP42 M 1 50k VDD = +2.7V VSS = 2.7V DATA = 40H VA = 50mV rms VB = 0V
100k 50k
VERSION VERSION
1
0k
10k FREQUENCY Hz
Figure 9.
VWB / T Potentiometer Mode Tempco
igure 12. Gain vs. Frequency vs. RAB
120 100 RHEOSTAT MODE TEMPCO ppm/ C 80 60 50k 40 20 0 20 40 60 80 0 16 32 48 64 80 CODE Decimal 96 112 128 1M VERSION 10k VERSION VERSION 100k VERSION VDD/VSS = 2.7V/0V TA = 25 C
10 FILTER = 22kHz VDD = 2.7V VIN = 1V rms TA = 25 C 1.0 THD + NOISE %
0.1 SEE TEST CIRCUIT FIGURE 25 SEE TEST CIRCUIT FIGURE 26
0.01
0.001 10 100 1k FREQUENCY Hz 10k 100k
Figure 10.
RWB / T Rheostat Mode Tempco
Figure 13. Total Harmonic Distortion Plus Noise vs. Frequency
0 NORMALIZED GAIN FLATNESS 0.1dB/DIV CODE = 3FH 10 20H 10H GAIN - dB 20 08H 04H 30 02H 01H 40 TA = 25 C SEE TEST CIRCUIT FIGURE 32 50 10 100 1k 10k 100k FREQUENCY Hz 1M 10M F 1M SEE TEST CIRUIT 27 VDD = 2.7V VSS = 2.7V VA = 50mV rms VB = 0V DATA = 40H A W OP42 00k 5 10k
1
0k
B 10 100 1k 10k FREQUENCY Hz 100k 1M
Figure 11. 10 k Gain vs. Frequency vs. Code
igure 14. Normalized Gain Flatness vs. Frequency
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