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Details, datasheet, quote on part number:AD5232BRU50
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FEATURES Nonvolatile Memory Preset Maintains Wiper Settings Dual Channel, 256-Position Resolution Full Monotonic Operation DNL < 1 LSB 10 k , 50 k , 100 k Terminal Resistance Linear or Log Taper Settings Push-Button Increment/Decrement Compatible SPI-Compatible Serial Data Input with Readback Function 3 V to 5 V Single Supply or 2.5 V Dual Supply Operation 14 Bytes of User EEMEM Nonvolatile Memory for Constant Storage Permanent Memory Write Protection 100-Year Typical Data Retention TA = 55 C APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment DIP Switch Setting GENERAL DESCRIPTION
8-Bit Dual Nonvolatile Memory Digital Potentiometer AD5232 *
FUNCTIONAL BLOCK DIAGRAM
CS CLK SDI GND SDI SERIAL INTERFACE ADDR DECODE RDAC1 REGISTER
AD5232
VDD RDAC1 A1 W1 EEMEM1 B1
SDO WP RDY PR
SDO EEMEM CONTROL 14 BYTES USER EEMEM
RDAC2 REGISTER
RDAC2 A2 W2
EEMEM2
B2 VSS
The AD5232 device provides a nonvolatile, dual-channel, digitally controlled variable resistor (VR) with 256-position resolution. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD5232's versatile programming via a microcontroller allows multiple modes of operation and adjustment. In the direct program mode a predetermined setting of the RDAC r e g i s t e r can be loaded directly from the microcontroller. Another key mode of operation allows the RDAC register to be refreshed with the setting previously stored in the EEMEM register. When changes are made to the RDAC register to establish a new wiper position, the value of the setting can be saved into the EEMEM by executing an EEMEM save operation. Once the settings are saved in the EEMEM register these values will be automatically transferred to the RDAC register to set the wiper position at system power ON. Such operation is enabled by the internal preset strobe and the preset can also be accessed externally. All internal register contents can be read out of the serial data output (SDO). This includes the RDAC1 and RDAC2 registers, the corresponding nonvolatile EEMEM1 and EEMEM2 registers, and the 14 spare USER EEMEM registers available for constant storage.
*Patent pending.
The basic mode of adjustment is the increment and decrement command controlling the present setting of the Wiper position setting (RDAC) register. An internal scratch pad RDAC register can be moved UP or DOWN one step of the nominal terminal resistance between terminals A and B. This linearly changes the wiper to B terminal resistance (RWB) by one position segment of the devices' end-to-end resistance (RAB). For exponential/logarithmic changes in wiper setting, a left/right shift command adjusts levels in ± 6 dB steps, which can be useful for audio and light alarm applications. The AD5232 is available in a thin TSSOP-16 package. All parts are guaranteed to operate over the extended industrial temperature range of 40°C to +85°C. An evaluation board is available, Part Number: AD5232EVAL.
100
PERCENT OF NOMINAL END-TO-END RESISTANCE % RAB
75
50
25 RWB 0 RWA
0
64
128 CODE Decimal
192
256
Figure 1. Symmetrical RDAC Operation
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD5232SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, 10 k , 50 k , 100 k
( VD D = 3 V
Parameter
VERSIONS
Min Typ1 Max Unit
10% or 5 V
10% and VSS = 0 V, VA = +VDD, VB = 0 V, 40 C < TA < +85 C unless otherwise noted.)
Symbol Conditions
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential Nonlinearity2 R-DNL Resistor Nonlinearity2 R-INL Nominal Resistor Tolerance R AB Resistance Temperature Coefficient RAB/ T Wiper Resistance RW RW
RWB, VA = NC RWB, VA = NC IW = 100 µA, VDD = 5.5 V, Code = 1EH IW = 100 µA, VDD = 3 V, Code = 1EH
1 0.4 40
± 1/2 600 5 200
+1 +0.4 +20 100
LSB % FS % p p m /° C Bits LSB % FS p p m /° C % FS % FS V pF pF µA V V V V V V V V µA pF
POTENTIOMETER DIVIDER MODE -- Specifications Apply to All VRs Resolution N Differential Nonlinearity3 DNL INL Integral Nonlinearity3 Voltage Divider Temperature Coefficient V W/ T Code = Half-Scale Full-Scale Error V WFSE Code = Full-Scale Code = Zero-Scale Zero-Scale Error VWZSE RESISTOR TERMINALS Terminal Voltage Range4 Capacitance5 Ax, Bx Capacitance5 Wx Common-Mode Leakage Current5, 6 DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High (SDO and RDY) Output Logic Low Input Current Input Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current7 Negative Supply Current Power Dissipation8 Power Supply Sensitivity5 VA,B,W CA,B CW ICM V IH V IL V IH V IL V IH V IL V OH V OL II L CIL VDD VDD/VSS IDD IDD(PG) IDD(XFR) IS S PD I S S PSS
8 1 0.4 3 0 V SS
± 1/2 15
+1 +0.4 0 +3 VDD
f = 1 MHz, Measured to GND, Code = Half-Scale f = 1 MHz, Measured to GND, Code = Half-Scale VW = VDD/2 With Respect to GND, VDD = 5 V With Respect to GND, VDD = 5 V With Respect to GND, VDD= 3 V With Respect to GND, VDD = 3 V With Respect to GND, VDD = +2.5 V, VSS = 2.5 V With Respect to GND, VDD = +2.5 V, VSS = 2.5 V RPULL-UP = 2.2 k to 5 V IOL = 1.6 mA, VLOGIC = 5 V VIN = 0 V or VDD 2.4
45 60 0.01
1
0.8 2.1 0.6 2.0 0.5 4.9 0.4 ± 2.5 4
V SS = 0 V VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = +2.5 V, VSS = 2.5 V VIH = VDD or VIL = GND VDD = 5 V ± 10%
2.7 ± 2.25 0.9 3.5 35 3 3.5 0.018 0.002
5.5 V ± 2.75 V 10 µA mA 9 mA 10 0.05 0.01 µA mW %/%
2
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AD5232
Parameter DYNAMIC CHARACTERISTICS Bandwidth Total Harmonic Distortion
5, 9
Symbol
Conditions 3 dB, BW_10 k, R = 10 k VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k VA =1 V rms, VB = 0 V, f = 1 kHz, RAB = 50 k, 100 k VDD = 5 V, VSS = 0 V, VA = VDD, VB = 0 V, VW = 0.50% Error Band, Code 00H to 80H For RAB = 10 k/50 k/100 k RWB = 5 k, f = 1 kHz Crosstalk (CW1/CW2) CT VA = VDD, VB = 0 V, Measure VW with Adjacent VR Making Full-Scale Code Change VA1 = VDD, VB1 = 0 V, Measure VW1 with VW2 = 5 V p-p @ f = 10 kHz, Code1 = 80H; Code2 = FFH
Min
Typ1 500 0.022 0.045
Max Unit kHz % % µs nV/ Hz nV-s
THDW THD W
VW Settling Time Resistor Noise Voltage
tS eN_WB
0.65/3/6 9
5
Analog Crosstalk (CW1/CW2)
CTA
70 20 10 1 10 5 5 40 50 50 0 10 4 0 0.1 10 50 70 100 100 0.15 25
dB ns ns tCYC ns ns ns ns ns ns ns ns tCYC ns ms ms ns ns µs K Cycles Years
INTERFACE TIMING CHARACTERISTICS Applies to All Parts5, 10 Clock Cycle Time (tCYC) t1 CS Setup Time t2 CLK Shutdown Time to CS Rise t3 Input Clock Pulsewidth t 4, t 5 Clock Level High or Low From Positive CLK Transition Data Setup Time t6 Data Hold Time t7 From Positive CLK Transition CS to SDO-SPI Line Acquire t8 CS to SDO-SPI Line Release t9 CLK to SDO Propagation Delay11 t 10 RP = 2.2 k, CL < 20 pF CLK to SDO Data Hold Time t 11 RP = 2.2 k, CL < 20 pF t 12 CS High Pulsewidth12 CS High to CS High12 t 13 RDY Rise to CS Fall t 14 CS Rise to RDY Fall Time t 15 Read/Store to Nonvolatile EEMEM13 t 16 Applies to Command 2H, 3H, 9H CS Rise to Clock Rise/Fall Setup t 17 Not Shown in Timing Diagram Preset Pulsewidth (Asynchronous) tP R W Preset Response Time to RDY High tPRESP PR Pulsed Low to Refreshed Wiper Positions FLASH/EE MEMORY RELIABILITY CHARACTERISTICS E n d u r a n c e1 4 Data Retention15
NOTES 1 Typical parameters represent average readings at 25°C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper postions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W ~ 50 µA @ VDD = 2.7 V and IW ~ 400 µA @ VDD = 5 V for the R AB = 10 k version, I W ~ 50 µA for the RAB = 50 k and I W ~ 25 µA for the RAB = 100 k version. See Figure 13. 3 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = VSS. DNL specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 14. 4 Resistor terminals A, B, W have no limitations on polarity with respect to each other. Dual Supply Operation enables ground-referenced bipolar signal adjustment. 5 Guaranteed by design and not subject to production test. 6 Common-mode leakage current is a measure of the dc leakage from any terminal A, B, W to a common-mode bias level of VDD/2. 7 Transfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9. 8 PDISS is calculated from (I DD VDD) + (ISS VSS). 9 All dynamic characteristics use V DD = +2.5 V and VSS = 2.5 V unless otherwise noted. 10 See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V DD = 3 V or 5 V. 11 Propagation delay depends on value of V DD, RPULL_UP, and C L. See applications text. 12 Valid for commands that do not activate the RDY pin. 13 RDY pin low only for instruction commands 8, 9, 10, 2, 3, and the PR hardware pulse: CMD_8 ~ 1 ms; CMD_9,10 ~ 0.12 ms; CMD_2,3 ~ 20 ms. Device operation at TA = 40°C and VDD < 3 V extends the save time to 35 ms. 14 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at V DD = 2.7 V, TA = 40°C to +85°C, typical endurance at 25°C is 700,000 cycles. 15 Retention lifetime equivalent at junction temperature (T J) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction temperature as shown in Figure 23 in the Flash/EE Memory description section of this data sheet. The AD5232 contains 9,646 transistors. Die size: 69 mil 115 mil, 7,993 sq. mil. Specifications subject to change without notice
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AD5232
CPHA = 1 CS
t12 t3 t2
CLK CPOL = 1
t13
t1 t5 t4 t10 t17 t11
LSB OUT
t8
SDO
t9
*
MSB
t7 t6
SDI MSB LSB
t14
RDY *NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
t15 t16
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2a. CPHA = 1 Timing Diagram
CS
CPHA = 0
t12 t1 t2
CLK CPOL = 0
t3 t5 t17
t13
t4
t8
t10
t11 t9
SDO
MSB OUT
LSB
*
t7 t6
SDI MSB IN LSB
t14
RDY *NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.
t15 t16
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2b. CPHA = 0 Timing Diagram
4
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AD5232
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, 7 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VA, VB, VW to GND . . . . . . . . . . . . . VSS 0.3 V, VDD + 0.3 V AX BX, AX WX, BX WX Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 2 mA Digital Inputs and Output Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD +0.3 V Operating Temperature Range3 . . . . . . . . . . . 40°C to +85°C Maximum Junction Temperature (TJ Max) . . . . . . . . 150°C Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Package Power Dissipation . . . . . . . . . . . . . (TJ Max TA)/ JA Thermal Resistance Junction-to-Ambient JA, TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W Thermal Resistance Junction-to-Case JC, TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 3 Includes programming of nonvolatile memory.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5232 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model AD5232BRU10 AD5232BRU10-REEL7 AD5232BRU50 AD5232BRU50-REEL7 AD5232BRU100 AD5232BRU100-REEL7
Number of Channels 2 2 2 2 2 2
End-to-End R AB (k ) 10 10 50 50 100 100
Temperature Package Package Range (°C) Description Option 40 to +85 40 to +85 40 to +85 40 to +85 40 to +85 40 to +85 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16
Number of Devices per Container 96 1,000 96 1,000 96 1,000
Branding* Information 5232B10 5232B10 5232B50 5232B50 5232BC 5232BC
*Line 1 contains ADI logo symbol and the data code YYWW, line 2 contains detail model number listed in this column.
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