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Details, datasheet, quote on part number:AD5235BRU250
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Datasheet text preview:
PRELIMINARY TECHNICAL DATA
a
FEATURES Dual, 1024 Position Resolution 25K, 250K Ohm Terminal Resistance with 50ppm/°C Tempco Nonvolatile Memory Preset SPI Compatible Serial Data Input with Readback Function Increment/Decrement Commands, Push Button Command +3 to +5V Single Supply Operation ±2.5V Dual Supply Operation 30 bytes of general purpose nonvolatile memory APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage to Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment DIP Switch Setting
Nonvolatile Memory, Dual 1024 Position Digital Potentiometers
AD5235
FUNCTIONAL BLOCK DIAGRAMS
RD A C1 CS CL K S DI S DO
SER IAL IN P U T R E G IS T E R
ADDRE S S DECO DE
V DD A1 W1 B1
RD A C1 RE GIS T E R
EEM EM 1
RD A C2 PR P W R ON P RE S E T RD A C2 RE GIS T E R
A2 W2 B2
WP R DY
E E M EM C ON TR OL
EEM EM 2
VSS
G ND S P A RE EEM EM
G ND
GENERAL DESCRIPTION
The AD5235 provides a dual channel, digitally controlled variable resistor (VR) with resolutions of 1024 positions. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD5235's versatile programming via a Micro Controller allows multiple modes of operation and adjustment. In the direct program mode a predetermined setting of the RDAC register can be loaded directly from the micro controller. Another key mode of operation allows the RDAC register to be refreshed with the setting previously stored in the EEMEM register. When changes are made to the RDAC register to establish a new wiper position, the value of the setting can be saved into the EEMEM by executing an EEMEM save operation. Once the settings are saved in the EEMEM register, these values will be transferred automatically to the RDAC register to set the wiper position at system power ON. Such operation is enabled by the internal preset strobe and the preset can also be accessed externally. An internal scratch pad RDAC register can be programmed by the micro controller to set the resistance between terminals W-and-B. Once the target value is achieved, the RDAC content register can be placed in the non-volatile memory for automatic recall during Power Up. The AD5235 is available in the thin TSSOP-16 package. All parts are guaranteed to operate over the extended industrial temperature range of -40°C to +85°C.
REV PrD 6 Nov 2000 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 Fax:781/326-8703
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers
= +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
AD5235
Min
-1 -2 -30 50 50 200
ELECTRICAL CHARACTERISTICS 25K, 250K OHM VERSIONS (VDD = +3V±10% or +5V±10% and VSS=0V, VA
Parameter
Resistor Differential NL2 Resistor Nonlinearity2 Nominal resistor tolerance Resistance Temperature Coefficent Wiper Resistance Wiper Resistance
Symbol
R-DNL R-INL R RAB/T RW RW N INL DNL VW/T VWFSE VWZSE VA,B,W CA,B CW ICM VIH VIL V OH V OH V OL IIL CIL VD D VDD/VSS IDD IDD(PG) IDD(READ) ISS PDISS PSS
Conditions
RWB, VA=NC RWB, VA=NC TA = 25°C, VAB = VDD,Wiper (VW) = No connect VAB = VDD, Wiper (VW) = No Connect IW = 1 V/R, VDD = +5V IW = 1 V/R, VDD = +3V
Typ
1
Max
+1 +2 30 100
Units
LSB LSB % ppm/°C
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs ±1/4 ±1/2
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution Integral Nonlinearity3 Differential Nonlinearity3 Voltage Divider Temperature Coefficent Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range4 Capacitance5 Ax, Bx Capacitance5 Wx Common-mode Leakage Current7 DIGITAL INPUTS & OUTPUTS Input Logic High Input Logic Low Output Logic High Output Logic High Output Logic Low Input Current Input Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current Negative Supply Current Power Dissipation6 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 7 Bandwidth 3dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Crosstalk BW_25K THDW tS eN_WB CT R = 12K VA =1Vrms, VB = 0V, f=1KHz VA= VDD, VB=0V, 50% of final value 25K/250K RWB = 10K, f = 1KHz VA = VDD, VB = 0V, Measue VW with adjacent VR making full scale change 400 0.003 0.6/3/6 9 -65 KHz % µs nVHz dB VSS = 0V VSS = 0V VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = 2.5V, VSS = -2.5V VIH = VDD or VIL = GND VDD = +5V ±10% 2.7 ±2.2 2 15 650 5.5 ±2.7 20 V V µA mA µA µA mW %/% with respect to GND with respect to GND RPULL-UP = 2.2K to +5V IOH = 40µA, VLOGIC = +5V IOL = 1.6mA, VLOGIC = +5V VIN = 0V or VDD 0.3·VDD 0.7·VDD 4.9 4 0.4 ±1 5 V V V V V µA pF VSS f = 1 MHz, measured to GND, Code = Half-scale f = 1 MHz, measured to GND, Code = Half-scale VA = VB = VDD/2 45 60 0.01 1 VDD V pF pF µA 10 2 1 Code = Half-scale Code = Full-scale Code = Zero-scale 3 0 ±1/2 ±1/4 15 -1 +1 +2 +1 +0 +3 Bits LSB LSB ppm/°C LSB LSB
10 0.002 0.05 0.01
REV PrD 6 NOV, 2000 2 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers
= +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
AD5235
Min 20 10 10 5 5 0 10 10 1 Typ
1
ELECTRICAL CHARACTERISTICS 25K, 250K OHM VERSIONS (VDD = +3V±10% to +5V±10% and VSS=0V, VA
Parameter Clock Cycle Time Input Clock Pulse Width CS Setup Time Data Setup Time Data Hold Time CLK Shutdown Time CS Rise to Clock Rise Setup CS High Pulse Width CLK to SDO Propagation Delay9 Store to Nonvolatile EEMEM Save Time10 CS to SDO - SPI line acquire CS to SDO - SPI line release RDY Rise to CLK Rise Startup Time CLK Setup Time Preset Pulse Width NOTES:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Typicals represent average readings at +25°C and VDD = +5V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit. IW = VDD/R for both VDD=+3V or VDD=+5V. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit. Resistor terminals A,B,W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. PDISS is calculated from (IDD x VDD=+5V). All dynamic characteristics use VDD = +5V. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching characteristics are measured using both VDD = +3V or +5V. Propagation delay depends on value of VDD, RPULL_UP, and CL see applications text. Low only for commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.1ms; CMD_2,3 ~20ms.
Symbol t1 t 2, t 3 t4 t5 t6 t7 t8 t9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 tPR
Conditions
Max
Units ns ns ns ns ns ns ns ns ns ms ns ns ns ms ns ns
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5, 8) Clock level high or low From Positive CLK transition From Positive CLK transition
RL = 1K, CL < 20pF Applies to Command 2H, 3H
25 25
For 1 CLK period (t4 - t3 = 1 CLK period) 50
Timing Diagram
CLK
t16 t4 t1 t3 t2 t8 t7 t9 t5 t6
CS
SDI
t12
MSB
t1 0
LSB
t1 3
SDO
1
MSB MSB
t1 4
LSB LSB
t1 5 t11
S D O2 RDY
S DO 1 CLK IDLES LOW
S DO 2 CLK IDLES HIGH
Figure 1. Timing Diagram
REV PrD 6 NOV, 2000 3 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers
Absolute Maximum Rating (TA = +25°C, unless otherwise
noted) VDD to GND.....-0.3, +7V VSS to GND ........ 0V, -7V VDD to VSS ....... +7V VA, VB, VW to GND ....... VSS, VDD AX BX, AX WX, BX WX ..... ±20mA Ox to GND..........0V, VDD Digital Inputs & Output Voltage to GND ......... 0V, +7V Operating Temperature Range....... -40°C to +85°C Maximum Junction Temperature (TJ MAX)..........+150°C Storage Temperature .... -65°C to +150°C Lead Temperature (Soldering, 10 sec)..+300°C Thermal Resistance JA, TSSOP-16...... 180°C/W
Package Power Dissipation = (TJMAX - TA) / JA
CLK SDI SDO GND VSS A1 W1 B1 1 2 3 4 5 6 7 8 15 CS 14 P R PR 13 W P WP 12 VDD 11 A2 10 W2 9 B2
AD5235
AD5235 PIN CONFIGURATION
16 RDY
AD5235 PIN FUNCTION DESCRIPTION # Name Description
1 2 CLK SDI SDO Serial Input Register clock pin. Shifts in one bit at a time on positive clock edges. Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 and 10 activate the SDO output. See Instruction operation Truth Table. Table 2. Ground pin, logic ground reference Negative Supply. Connect to zero volts for single supply applications. A terminal of RDAC1. Wiper terminal of RDAC1, ADDR(RDAC1) = 0H. B terminal of RDAC1. B terminal of RDAC2. Wiper terminal of RDAC2, ADDR(RDAC3) = 1H. A terminal of RDAC2. Positive Power Supply Pin. Should be the input-logic HIGH voltage. Write Protect Pin. Prevents any changes to the present EEMEM contents when active low. Hardware over ride preset pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 51210. Serial Register chip select active low. Serial register operation takes place when CS returns to logic high. Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10.
Ordering Guide
Model #CHs/ k Ohm Temp Range Package Package Description Option
RU-16 RU-16
3
AD5235BRU25 X2/25 AD5235BRU250 X2/250
-40/+85°C TSSOP-16 -40/+85°C TSSOP-16
4 5 6 7 8 9 10 11 12 13 14
GND V SS A1 W1 B1 B2 W2 A2 VDD WP PR
The AD5235 contains 16,000 transistors. Die size: 100 x 105 mil = 10,500 sq. mil
15
CS
16
RDY
REV PrD 6 NOV, 2000 4 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers
OPERATIONAL OVERVIEW
The AD5235 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of VSS
AD5235
Permanent storage of the present scratch pad RDAC register values into the corresponding EEMEM register 30 bytes of user addressable electrical-erasable memory
The serial interface of AD5235 digital potentiometer uses a 24-bit serial word loaded with MSB first. The format of the SPI compatible word is shown in Table 1. The Command Bits (Cx) control the operation of the digital potentiometer according to the command instruction shown in Table 2. The Address Bits (Ax) determine which register is activated. The Data Bits (Dx) are the values that are loaded into the decoded register. The last instruction executed prior to a period of no programming activity should be the NOP instruction. This will place the internal logic circuitry in a minimum power dissipation state.
PR
V A L ID CO MMAND CO UNTER CO MMAND PROCESSOR & ADDRESS DECODE
+5V R PULLUP
C LK
S E R IA L R E G IS T E R
SDO CS SDI GND
Figure 2. Equivalent Digital Input-Output Logic The equivalent serial data input and output logic is shown in figure 2. The open drain output SDO is disabled whenever chip select CS is logic high. The SPI interface can be used in two slave modes CPHA=1, CPOL=1 and CPHA=0, CPOL=0. CPHA and CPOL refer to the control bits, which dictate SPI timing in the following microprocessors/MicroConverters: ADuC812/824, M68HC11, and MC68HC16R1/916R1.
Table 1. AD5235 24-bit Serial Data Word M S B AD5235 C3 C2 C1 C0 A3 A2 A1 A0 X X X X X X D9 D8 D7 D6 D5 D4 Command bits are identified as Cx, address bits are Ax, and data bits are Dx. Command instruction codes are defined in table 2.
D3
D2
D1
L S B D0
REV PrD 6 NOV, 2000 5 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
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