FEATURES 256 Position , 100 Low Tempco 30 ppm/ C Internal Power ON Midscale Preset Single Supply V or Dual Supply 2.7 V for AC or Bipolar Operation I2C-Compatible Interface with Reaback Capability Extra Programmable Logic Outputs APPLICATIONS Multimedia, Video and Audio Communications Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Line Impedance Matching GENERAL DESCRIPTION
The AD5241/AD5242 provides a single-/dual-channel, 256position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer, trimmer or variable resistor. Each VR offers a completely programmable value of resistance, between the A terminal and the wiper, or the B terminal and the wiper. For AD5242, the fixed A-to-B terminal resistance 1 M has a 1% channel-to-channel matching tolerance. Nominal temperature coefficient of both parts is 30 ppm/°C. Wiper position programming defaults to midscale at system power ON. Once powered, the VR wiper position is programmed I2C-compatible 2-wire serial data interface. Both parts have available two extra programmable logic outputs that enable users to drive digital loads, logic gates, LED drivers, and analog switches in their system. The AD5241/AD5242 is available in surface-mount (SO-14/-16) packages and, for ultracompact solutions, TSSOP-14/-16 packages. All parts are guaranteed to operate over the extended industrial temperature range to +85°C. For 3-wire, SPI-compatible interface applications, please refer AD8400, AD8402, and AD8403 products.
*Nonvolatile digital potentiometer. is a registered trademark of Philips Corporation.
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Conditions Min Typ1 Max Unit LSB % ppm/°C Bits LSB ppm/°C LSB µA µW kHz % µs nVHz
DC CHARACTERISTICS, RHEOSTAT MODE (Specifications apply to all VRs.) Resistor Differential Nonlinearity 2 R-DNL RWB, = NC Resistor Integral Nonlinearity2 R-INL RWB, = NC Nominal Resistor Tolerance = 25°C, RAB = 25°C, RAB k/1 M Resistance Temperature Coefficient RAB/T VAB = VDD, Wiper = No Connect Wiper Resistance IW = VDD /R, VDD V DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.) Resolution N Differential Nonlinearity3 DNL Integral Nonlinearity3 INL Voltage Divider Temperature Coefficient VW/T Code = 80H Full-Scale Error VWFSE Code = FFH Zero-Scale Error VWZSE Code = 00H RESISTOR TERMINALS Voltage Capacitance5 W Common-Mode Leakage DIGITAL INPUTS Input Logic High (SDA and SCL) Input Logic Low (SDA and SCL) Input Logic High (AD0 and AD1) Input Logic Low (AD0 and AD1) Input Logic High Input Logic Low Input Current Input Capacitance5 DIGITAL OUTPUT Output Logic Low (SDA) Output Logic Low (O1 and O2) Output Logic High (O1 and O2) Three-State Leakage Current (SDA) Output Capacitance5 POWER SUPPLIES Power Single-Supply Range Power Dual-Supply Range Positive Supply Current Negative Supply Current Power Dissipation6 Power Supply Sensitivity DYNAMIC 7, 8 Bandwidth 3 dB VA, B, W CA, B CW ICM VIH VIL VIH VIL VIH VIL IIL CIL VOL VOH IOZ COZ VDD RANGE VDD/SS RANGE IDD ISS PDISS PSS BW_1 M THDW tS eN_WB
= 1 MHz, Measured to GND, Code = 1 MHz, Measured to GND, Code VW 0.7 VDD
0.01 RAB 10 k, Code = 80H RAB 100 k, Code = 80H RAB 1 M, Code 1 V rms 2 V dc, 2 V dc, = 1 kHz VA = VDD, ± 1 LSB Error Band, RAB 10 k RWB = 1 kHz
Total Harmonic Distortion VW Settling Time Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS (Applies to all parts. ) SCL Clock Frequency fSCL tBUF Bus Free Time Between t1 STOP and START tHD; STA Hold Time (Repeated START) t2 After this period the first clock pulse is generated. tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU; STA Setup Time for START Condition t5 t6 tHD; DAT Data Hold Time tSU; DAT Data Setup Time t7 tR Rise Time of Both t8 SDA and SCL Signals tF Fall Time of Both SDA and SCL Signals t9 tSU; STO Setup Time for STOP Condition t10
NOTES 1 Typicals represent average readings at 25 °C, VDD V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 10 test circuit. 3 INL and DNL are measured V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. A = VDD and 0 V. DNL specification limits ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 9 test circuit. 4 Resistor terminals B, W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 7 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 8 All dynamic characteristics use V. 9 See timing diagram for location of measured values. Specifications subject to change without notice.