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Part: AD5263BRU50-REEL7
Category:
Description: +15 V, Quad, 256 Position, Digital Potentiometer
Company: Analog Devices
Datasheet: Download AD5263BRU50-REEL7 datasheet File size : 845 kB
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a
Quad +15V 256-Position Digital Potentiometer with Pin Selectable SPI/I2C Digital Interface
Preliminary Technical Data
FEATURES 4-Channel 256-Position End-to-End Resistance 20k, 50k, 200k 2 Pin Selectable SPI or I C Compatible Interface Two Package Address Decode Pins AD0 and AD1 Low Temperature Coefficient 30ppm/oC Wide Operating Temperature Range -40 to 125ºC +5 to +15V Single-Supply; ±7.5V Dual-Supply Operation APPLICATIONS Mechanical Potentiometer Replacement Optical Network Adjustment Instrumentation: Gain, Offset Adjustment Stereo Channel Audio Level Control Automotive Electronics Adjustment Programmable Voltage to Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Low Resolution DAC Replacement Motor Control GENERAL DESCRIPTION The AD5263 is the industries first quad channel, 256 1 position, digital potentiometer with a selectable digital interface. These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. Each channel of the AD5263 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code 2 loaded into the 3-wire SPI or 2-wire I C compatible serialinput register. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC latch. The variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 20k, 50k or 200k has a nominal temperature coefficient of 30 ppm/°C. Unlike the majority of the digital potentiometers in the market, these devices can operate up to +15V or ±7.5V. The AD5263 is available in narrow body TSSOP-24. All parts are guaranteed to operate over the automotive temperature range of -40°C to +125°C. NOTE
1. The terms digital potentiometer, VR, and RDAC are used interchangeably.
AD5263
Functional Block Diagram
A1 VDD VSS SH DN RS /AD1 W1 B1 A2 W2 B2 A3 W3 B3 A4 W4 B4
RDAC 1 REGISTER
RDAC 2 REGISTER
RDAC 3 REGISTER
RDAC 4 REGISTER
VL
8
AD5263
CLK /SCL SDI / SDA CS /AD0
ADDRESS DECODER SPI / I2C SELECT LOGIC
SERIAL INPUT REGISTER
GND DIS NC / O2 SDO / O1
100% R W A(D ), R W B (D ) -% of Nom i n a l R AB RW A 75% RW B
50%
25%
0% 0 64 128
C O DE - De c i m a l
192
255 256
RWA and RWB vs. Code
REV. PrE 1/23/03 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2003
Preliminary Technical Data
VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.)
AD5263
Min
-1 -2 -30 30 50
ELECTRICAL CHARACTERISTICS 20k, 50k, 200k VERSION (VDD = +5V, VSS = -5V, VL = +5V,
Parameter
Resistor Differential NL2 Resistor Nonlinearity2 Nominal resistor tolerance3 Resistance Temperature Coefficient Wiper Resistance
Symbol
R-DNL R-INL RAB RAB/T RW N DNL INL VW/T VWFSE VWZSE VA,B,W C A,B CW ICM VI H VI L VI H VI L IIL C IL
Conditions
RWB, VA=NC RWB, VA=NC TA = 25°C Wiper = No Connect IW = 1 V/RAB, VDD = +5V
Typ1
±1/4 ±1/2
Max
+1 +2 30 100
Units
LSB LSB % ppm/°C
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution Differential Nonlinearity4 Integral Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range5 Capacitance6 Ax, Bx Capacitance6 Wx Common-Mode Leakage DIGITAL INPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance6 2.4 0.8 VL = +3V, VSS = 0V VL = +3V, VSS = 0V VIN = 0V or +5V 2.1 0.6 ±1 5 V V V V µA pF VSS f = 1 MHz, measured to GND, Code = 80H f = 1 MHz, measured to GND, Code = 80H VA =VB = VDD / 2 TBD TBD 1 VDD V pF pF nA 1 2 Code = 80H Code = FFH Code = 00H 2 0 ±1/4 ±1/2 5 -1 +1 8 +1 +2 +0 +2 Bits LSB LSB ppm/°C LSB LSB
DIGITAL Output O1, O2 O1, O2 SDO SDO Three-State Leakage Current Output Capacitance6
POWER SUPPLIES Logic Supply Power Single-Supply Range Power Dual-Supply Range Logic Supply Current Positive Supply Current Negative Supply Current Power Dissipation9 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 10 Bandwidth 3dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage BW THDW tS eN_WB RAB = 20k/50k/200k VA =1Vrms, VB = 0V, f=1KHz, RAB = 20K VA= 10V, VB=0V, ±1 LSB error band RWB = 10K, f = 1KHz, RS = 0
400/TBD/TBD
VOH VOL VOL VOL IO Z CO Z
VL VDD RANGE VDD/SS RANGE IL IDD ISS P DISS PSS
IOH=0.4mA, I2C Mode IOL=-1.6mA, I2C Mode IOL = -6mA IOL = -3mA VIN = 0V or +5V
2.4 0
3
2.7 4.5 ±4.5
5.5 0.4 0.6 0.4 ±1 8
5.5 16.5 ±7.5 60 1 1 0.6 0.01
V V
V V µA pF
V V V µA µA µA mW %/%
VSS = 0V VL = +5V VIH = +5V or VIL = 0V VSS = -5V VIH = +5V or VIL = 0V, VDD = +5V, VSS = -5V VDD = +5V ±10%
0.002
0.05 2 9
KHz % µs nVHz
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Preliminary Technical Data
VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.)
AD5263
Min Typ1 Max 25 Units MHz ns ns ns ns ns ns ns ns ns KHz µs µs µs µs µs µs ns ns ns µs
ELECTRICAL CHARACTERISTICS 20k, 50k, 200k VERSION (VDD = +5V, VSS = -5V, VL = +5V,
Parameter Symbol fCLK tCH,tCL tDS tDH tCSS tCSW tCSH0 tCSH1 tCS1 tRS Conditions SPI INTERFACE TIMING CHARACTERISTICS applies to all parts (Notes 6,10) Clcok Frequency Input Clock Pulse Width Data Setup Time Data Hold Time CS Setup Time CS High Pulse Width CLK Fall to CS Fall Hold Time CLK Fall to CS Rise Hold Time CS Rise to Clock Rise Setup Reset Pulsewidth Clock level high or low 20 10 10 15 20 0 0 10 5 400 1.3 0.6 1.3 0.6 0.6 100 300 300 0.6
I2C INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12) SCL Clock Frequency fSCL tBUF Bus free time between STOP & START t1 tHD;STA Hold Time (repeated START) t2 After this period the first clock pulse is generated tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU;STA Setup Time For START Condition t5 tHD;DAT Data Hold Time t6 tSU;DAT Data Setup Time t7 tF Fall Time of both SDA & SCL signals t8 tR Rise Time of both SDA & SCL signals t9 tSU;STO Setup time for STOP Condition t10 NOTES:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
50 0.9
Typicals represent average readings at +25°C and VDD = +5V, VSS = -5V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD=+5V, VSS=-5V. VAB = VDD, Wiper (VW) = No connect INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. Resistor terminals A, B, W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. Worst case supply current consumed when input all logic-input levels set at 2.4V, standard characteristic of CMOS logic. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. All dynamic characteristics use VDD = +5V, VSS = -5V, VL = +5V. Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics are measured using VL = +5V. Propagation delay depends on value of VDD, RL, and CL. The AD5263 contains 5,184 transistors. Die Size: 108mil x 198mil, 21,384sq. mil.
REV. PrE 1/23/03
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Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS1 (TA = +25°C, unless otherwise noted) VDD to GND........-0.3, +16.5V VSS to GND....... 0V, -7.5V VDD to VSS .... +16.5V VL to GND ...... -0.3, +6.5V VA, VB, VW to GND........... VSS, VDD AX BX, AX WX, BX WX Intermittent2........... ±20mA Continuous..... ±5mA Digital Inputs & Output Voltage to GND .... 0V, +7V Operating Temperature Range ...... -40°C to +85°C Maximum Junction Temperature (TJ MAX) .. +150°C Storage Temperature .... -65°C to +150°C Lead Temperature (Soldering, 10 sec)....... +300°C Vapor Phase (60 sec)...... +215 °C Infrared (15 sec) ..... +220 °C Thermal Resistance3 JA, TSSOP-24 ...... 143°C/W
NOTES 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance 3. Package Power Dissipation (TJMAX-TA)/ JA
AD5263
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5263 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. PrE 1/23/03
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Preliminary Technical Data
AD5263 PIN CONFIGURATION
B1 A1 W1 B3 A3 W3 VDD GND DIS VLOGIC SDI/SDA 1 2 3 4 5 6 7 8 9 10 11 AD5263 TSSOP-24 24 B2 23 A2 22 W2 21 B4 20 A4 19 W4 18 VSS 17 NC/O2 16 SDO/O1 15 SHDN 14 RS/AD1 13 CS/AD0
AD5263
8 9 GND DIS Ground Digital Interface Select (SPI/I2C Select); SPI when DIS='0', I2C when DIS='1' Logic Supply Voltage, needs to be same voltage as the digital logic controlling the AD5263. SDI = 3-wire Serial Data Input/ SDA = 2-wire Serial Data Input/Output Serial Clock Input Chip Select / I2C Compatabile Device Address Bit 0 RESETB/I2C Compatabile Device Address Bit 1 Shutdown -- Ties wiper to terminal A, opens terminal B Serial Data Output, Open Drain transistor requires pull-up resistor/Digital Output O1, can be used to drive external logic No Connection/Digital Output O2, can be used to drive external logic Negative power supply, specified for operation from 0 to -5V. Wiper terminal W4 (ADDR=11) Resistor terminal A4 Resistor terminal B4 Wiper terminal W2 (ADDR=01) Resistor terminal A2 Resistor terminal B2
10
VLOGIC
11 12 13 14 15 16
SDI/SDA CLK/SCL CS/AD0 RS/AD1 SHDN SDO/O1
CLK/SCL 12
TABLE VII: AD5263 PIN Descriptions Pin Name Description
1 2 3 4 5 6 7 B1 A1 W1 B3 A3 W3 VDD Resistor terminal B1 Resistor terminal A1 (ADDR=00) Wiper terminal W1 Resistor terminal B3 Resistor terminal A3 Wiper terminal W3 (ADDR=10) Positive power supply, specified for +5V to +15V operation
17 18 19 20 21 22 23 24
NC/O2 VSS W4 A4 B4 W2 A2 B2
Model AD5263BRU20 AD5263BRU20-REEL7 AD5263BRU50 AD5263BRU50-REEL7 AD5263BRU200 AD5263BRU200-REEL7
RAB (k) 20 20 50 50 200 200
Temp -40/+125°C -40/+125°C -40/+125°C -40/+125°C -40/+125°C -40/+125°C
Package Description TSSOP-24 TSSOP-24 TSSOP-24 TSSOP-24 TSSOP-24 TSSOP-24
Package Option RU-24 RU-24 RU-24 RU-24 RU-24 RU-24
# Parts per Container 62 1,000 62 1,000 62 1,000
Top Mark* AD5263B20 AD5263B20 AD5263B50 AD5263B50 AD5263B200 AD5263B200
*Line 1 contains part number, line 2 contains ADI logo followed by the end-to-end resistance, line 3 contains date code YWW.
REV. PrE 1/23/03
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