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Details, datasheet, quote on part number:AD5280BRU20
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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES 256 Position AD5280 1-Channel AD5282 2-Channel (Independently Programmable) Potentiometer Replacement 20K, 50K, 200K Ohm with TC < 50ppm/ºC Internal Power ON Mid-Scale Preset +5 to +15V Single-Supply; ±5.5V Dual-Supply Operation I2C Compatible Interface APPLICATIONS Multi-Media, Video & Audio Communications Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage to Current Conversion Line Impedance Matching
A1 SHDN VDD VSS VL
+15V, I2C Compatible Digital Potentiometers
AD5280/AD5282
W1 B1 A2 W2 B2 O1 OUTPUT REGISTER
R
RDAC1 REGISTER
R
RDAC2 REGISTER
R
ADDRESS DECODE
AD5282
8
PWR ON RESET
SCL SDA GND AD0
SERIAL INPUT REGISTER
GENERAL DESCRIPTION
The AD5280/AD5282 provides a single/dual channel, 256 position digitally-controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer, trimmer or variable resistor. Each VR offers a completely programmable value of resistance, between the A terminal and the wiper, or the B terminal and the wiper. The fixed A-to-B terminal resistance of 20, 50 or 200K ohms has a 1% channel-to-channel matching tolerance with a nominal temperature coefficient of 30 ppm/°C. Wiper Position programming defaults to midscale at system power ON. Once powered the VR wiper position is programmed by a I2C compatible 2-wire serial data interface. Both parts have two programmable logic outputs available to drive digital loads, gates, LED drivers, analog switches, etc.
AD1
The AD5280/AD5282 are available in ultra compact surface mount thin TSSOP-14/-16 packages. All parts are guaranteed to operate over the extended industrial temperature range of -40°C to +85°C. For 3-wire, SPI compatible interface applications, see AD5203/AD5204/AD5206/AD7376/AD8400/AD8402/AD8403/ AD5260/AD5262/AD5200/AD5201 products.
ORDERING GUIDE
Model
AD5280BRU20 AD5280BRU50 AD5280BRU200 AD5282BRU20 AD5282BRU50 AD5282BRU200
Kilo Ohms
20 50 200 20 50 200
Temp
-40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C
Package Description
TSSOP-14 TSSOP-14 TSSOP-14 TSSOP-16 TSSOP-16 TSSOP-16
Package Option
RU-14 RU-14 RU-14 RU-16 RU-16 RU-16
FUNCTIONAL BLOCK DIAGRAMS
A1 W1 B1 O1 O2
SHDN
The AD5280/AD5282 die size is 75 mil X 120 mil, 9,000 sq. mil. Contains xxx transistors. Patent Number xxx applies.
RDAC1 REGISTER
R
VDD VSS VL ADDRESS DECODE RDAC2 REGISTER
R
AD5280
8
PWR ON RESET
SCL SDA GND AD0
SERIAL INPUT REGISTER
AD1
REV PrE 12 MAR 02 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 www.analog.com ©Analog Devices, Inc., 2002
AD5280/AD5282
Parameter Resistor Differential NL2 Resistor Nonlinearity2 Nominal resistor tolerance3 Resistance Temperature Coefficient Wiper Resistance Resolution Integral Nonlinearity4 Integral Nonlinearity4 Differential Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range5 Capacitance6 A, B Capacitance6 W Common Mode Leakage DIGITAL INPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance6 DIGITAL Output O1, O2 O1, O2 SDA SDA Three-State Leakage Current Output Capacitance6 POWER SUPPLIES
Logic Supply Power Single-Supply Range Power Dual-Supply Range
PRELIMINARY TECHNICAL DATA
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (VDD = +5V, VSS = -5V, VLOGIC = +5V,
VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Symbol R-DNL R-INL R RAB/T RW N INL INL DNL VW/T VWFSE VWZSE VA,B,W CA,B CW ICM VIH VIL VIH VIL VIH VIL IIL CIL VOH VOL VOL VOL IOZ COZ
Conditions RWB, VA=NC RWB, VA=NC TA = 25°C VAB = VDD, Wiper = No Connect IW = VDD /R, VDD = +3V or +5V
Min -1 -1 -30
Typ
1
Max +1 +1 30 100
Units LSB LSB % ppm/°C Bits LSB LSB LSB ppm/°C LSB LSB V pF pF nA V V V V V V µA pF
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs ±0.4 ±0.5 30 40 8 1 2 1 1 0 VSS f = 1 MHz, measured to GND, Code = 80H f = 1 MHz, measured to GND, Code = 80H VA = VB = VW SDA & SCL SDA & SCL AD0 & AD1 AD0 & AD1 VLOGIC = +3V, AD0 & AD1 VLOGIC = +3V, AD0 & AD1 VIN = 0V or +5V 0.7VLOGIC -0.5 2.4 0 2.1 0 3 IOH=0.4mA IOL=-1.6mA IOL = -6mA IOL = -3mA VIN = 0V or +5V 2.4 0 5.5 0.4 0.6 0.4 ±1 8
+5.5 +15 ±5.5
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs RAB=20K, 50K RAB=200K Code = 80H Code = FFH Code = 00H ±0.5 ±0.5 ±0.4 5 -0.5 +0.5 +1 +2 +1 +0 +1 VDD 45 60 1 VLOGIC+0.5 0.3VLOGIC VLOGIC 0.8 VLOGIC 0.6 ±1
V V
3
+2.7 +5 ±4.5
V V µA pF
V V V
VLOGIC VDD RANGE VSS = 0V VDD/SS RANGE
Logic Supply Current Positive Supply Current Negative Supply Current Power Dissipation10 Power Supply Sensitivity
ILOGIC IDD ISS PDISS PSS
VLOGIC = +5V VIH = +5V or VIL = 0V VIH = +5V or VIL = 0V, VDD = +5V, VSS = -5V
20 20 0.2 0.05
10 60 60 0.6 0.015
µA µA µA mW %/%
2
REV PrE 12 MAR 02
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
AD5280/AD5282
Typ
1
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (VDD = +5V, VSS = -5V, VLOGIC = +5V,
Parameter DYNAMIC CHARACTERISTICS6,9,11 Bandwidth 3dB BW_20K BW_50K BW_200K THDW tS eN_WB RAB = 20K, Code = 80H RAB = 50K, Code = 80H RAB = 200K, Code = 80H VA =1Vrms + 2V dc, VB = 2V DC, f=1KHz VA= VDD, VB=0V, ±1 LSB error band RWB = 10K, f = 1KHz 650 142 69 0.005 2 14 kHz kHz kHz % µs nVHz Symbol Conditions Min Max Units
Total Harmonic Distortion VW Settling Time Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12) SCL Clock Frequency tBUF Bus free time between STOP & START tHD;STA Hold Time (repeated START) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time For START Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of both SDA & SCL signals tR Rise Time of both SDA & SCL signals tSU;STO Setup time for STOP Condition NOTES:
1. 2. 3. 4. 5. 6. 9. 10. 11. 12. Typicals represent average readings at +25°C, VDD = +5V, VSS = -5V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. VAB = VDD, Wiper (VW) = No connect INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. Resistor terminals A,B,W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value result in the minimum overall power consumption. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. All dynamic characteristics use VDD = +5V. See timing diagram for location of measured values.
fSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
After this period the first clock pulse is generated
0 1.3 0.6 1.3 0.6 0.6 0 100
400
0.9 300 300
0.6
KHz µs µs µs µs µs µs ns ns ns µs
REV PrE 12 MAR 02
3
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
AD5280/AD5282
PRELIMINARY TECHNICAL DATA
TABLE 1: AD5280 PIN Function Descriptions Pin Name Description
1 2 3 4 5 A W B V DD SHDN Resistor terminal A Wiper terminal W Resistor terminal B Positive power supply, specified for operation from +5 to +15V. Active Low, Asynchronous connection of the wiper W to terminal B, and open circuit of terminal A. RDAC register contents unchanged. Serial Clock Input Serial Data Input/Output Programmable address bit for multiple package decoding. Bits AD0 & AD1 provide 4 possible addresses. Programmable address bit for multiple package decoding. Bits AD0 & AD1 provide 4 possible addresses. Common Ground Negative power supply, specified for operation from 0 to -5V Logic Output terminal O2 Logic Supply Voltage, needs to be same voltage as the digital logic controlling the AD5280. Logic Output terminal O1
ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless otherwise noted) VDD to GND .... -0.3, +15V VSS to GND ......... 0V, -7V VDD to VSS .... +15V VA, VB, VW to GND ......... VSS, VDD AX BX, AX WX, BX WX ........±20mA Digital Input Voltage to GND........0V, 7V Operating Temperature Range ...-40°C to +85°C Thermal Resistance* JA, TSSOP-14 ........206°C/W TSSOP-16 ........180°C/W Maximum Junction Temperature (TJ MAX) ........... +150°C Storage Temperature .......-65°C to +150°C Lead Temperature RU-14, RU-16 (Vapor Phase, 60 sec) ..... +215°C RU-14, RU-16 (Infrared, 15 sec) ...... +220°C
*
6 7 8
SCL SDA AD0
9
AD1
Package Power Dissipation (TJMAX - TA) / JA
10 11
AD5280 PIN CONFIGURATION
A W B VD D SHDN S HD N SCL SDA 1 2 3 4 5 6 7 14 13 12 11 10 9 8 O1 VL O2 VS S GND AD1 AD0
GND VSS O2 VL
12 13
14
O1
AD5282 PIN CONFIGURATION
O1 A1 W1 B1 VD D SHDN SHDN SCL SDA 1 2 3 4 5 6 7 8 16 A2 15 W2 14 B2 13 VL 12 V SS 11 GND 10 AD1 9 AD0
4
REV PrE 12 MAR 02
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
TABLE 2: AD5282 PIN Function Descriptions Pin Name Description
1 2 3 4 5 6 O1 A1 W1 B1 V DD SHDN Logic Output terminal O1 Resistor terminal A1 Wiper terminal W1 Resistor terminal B1 Positive power supply, specified for operation from +5 to +15V. Active Low, Asynchronous connection of the wiper W to terminal B, and open circuit of terminal A. RDAC register contents unchanged. Serial Clock Input Serial Data Input/Output 9 AD0
10
AD1
11 12 13
GND VSS VL
Programmable address bit for multiple package decoding. Bits AD0 & AD1 provide 4 possible addresses. Programmable address bit for multiple package decoding. Bits AD0 & AD1 provide 4 possible addresses. Common Ground Negative power supply, specified for
AD5280/AD5282
7 8
SCL SDA
14 15 16
B2 W2 A2
operation from 0 to -5V Logic Supply Voltage, needs to be same voltage as the digital logic controlling the AD5282. Resistor terminal B2 Wiper terminal W2 Resistor terminal A2
t8
SDA
t1 t8 t9 t6
SCL
t2
P S
t3
t4
t5
Sr
t7
P
t 10
Figure 1. Detail Timing Diagram Data of AD5280/AD5282 is accepted from the I2C bus in the following serial format:
S 0 1 0 1 1 A D 1 A D 0 R/ W A A/ B R S S D O 1 O 2 X X X A D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A P
Slave Address Byte Where: S = Start Condition P = Stop Condition A = Acknowledge X = Don't Care AD1, AD0 = Package pin programmable address bits
1 SCL S DA
S TA R T BY M AS T E R
Instruction Byte
Data Byte
R/W= Read Enable at High and Write Enable at Low W A/B = RDAC sub address select. "Zero" for RDAC1 and "One" for RDAC2 SD = Shutdown, same as SHDN pin operation except inverse logic O2, O1 = Output logic pin latched values D7,D6,D5,D4,D3,D2,D1,D0 = Data Bits
9
1 9
9
1
0
1
0
1
1
AD1
A D0
R /W ACK . BY A D 5 28 0
A /B
RS
SD
O1
O2
X
X
X
D7 ACK . BY A D 5 28 0
D6
D5
D4
D3
D2
D1
D0
A CK . B Y A D5 2 8 0
F RA M E 1 S l a ve A d dre s s B yt e
FRA ME 2 I nstru c t io n B yte
F RA M E 3 Da ta B yt e
Figure 2. Writing to the RDAC Register
REV PrE 12 MAR 02
5
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
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